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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Diff between revs 4 and 17

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Rev 4	Rev 17
Line 82...	Line 82...
`endmodule`	`endmodule`
`endif // ALTERA	`endif // ALTERA
`endif //ACTEL	`endif //ACTEL

`// sync reset`	`// sync reset`
`// input active lo async reset, normally from external reset generetaor and/or switch`	`// input active lo async reset, normally from external reset generator and/or switch`
`// output active high global reset sync with two DFFs`	`// output active high global reset sync with two DFFs`
`timescale 1 ns/100 ps	`timescale 1 ns/100 ps
`module vl_sync_rst ( rst_n_i, rst_o, clk);`	`module vl_sync_rst ( rst_n_i, rst_o, clk);`
`input rst_n_i, clk;`	`input rst_n_i, clk;`
`output rst_o;`	`output rst_o;`
`reg [0:1] tmp;`	`reg [0:1] tmp;`
`always @ (posedge clk or negedge rst_n_i)`	`always @ (posedge clk or negedge rst_n_i)`
`if (!rst_n_i)`	`if (!rst_n_i)`
`tmp <= 2'b00;`	`tmp <= 2'b11;`
`else`	`else`
`tmp <= {1'b1,tmp[0]};`	`tmp <= {1'b0,tmp[0]};`
`vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));`	`vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));`
`endmodule`	`endmodule`

`// vl_pll`	`// vl_pll`
`ifdef ACTEL	`ifdef ACTEL
`timescale 1 ns/100 ps	`timescale 1 ps/1 ps
`module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);`	`module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);`
`parameter index = 0;`	`parameter index = 0;`
`parameter number_of_clk = 1;`	`parameter number_of_clk = 1;`
`parameter period_time_0 = 20;`	`parameter period_time_0 = 20000;`
`parameter period_time_1 = 20;`	`parameter period_time_1 = 20000;`
`parameter period_time_2 = 20;`	`parameter period_time_2 = 20000;`
`parameter lock_delay = 2000;`	`parameter lock_delay = 2000000;`
`input clk_i, rst_n_i;`	`input clk_i, rst_n_i;`
`output lock;`	`output lock;`
`output reg [0:number_of_clk-1] clk_o;`	`output reg [0:number_of_clk-1] clk_o;`
`output [0:number_of_clk-1] rst_o;`	`output [0:number_of_clk-1] rst_o;`

Line 203...	Line 203...
`ifdef ALTERA	`ifdef ALTERA

`else	`else

`// generic PLL`	`// generic PLL`
`timescale 1 ns/100 ps	`timescale 1 ps/1 ps
`module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);`	`module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);`
`parameter index = 0;`	`parameter index = 0;`
`parameter number_of_clk = 1;`	`parameter number_of_clk = 1;`
`parameter period_time_0 = 20;`	`parameter period_time_0 = 20000;`
`parameter period_time_1 = 20;`	`parameter period_time_1 = 20000;`
`parameter period_time_2 = 20;`	`parameter period_time_2 = 20000;`
`parameter lock_delay = 2000;`	`parameter lock_delay = 2000;`
`input clk_i, rst_n_i;`	`input clk_i, rst_n_i;`
`output lock;`	`output lock;`
`output reg [0:number_of_clk-1] clk_o;`	`output reg [0:number_of_clk-1] clk_o;`
`output [0:number_of_clk-1] rst_o;`	`output [0:number_of_clk-1] rst_o;`
Line 241...	Line 241...

`endmodule`	`endmodule`

`endif //altera	`endif //altera
`endif //actel	`endif //actel
`No newline at end of file`	`No newline at end of file`

`No newline at end of file`	`No newline at end of file`

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Diff between revs 4 and 17