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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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Rev 104 |
Line 78... |
Line 78... |
q <= {q[length-1],q[0:length-2]};
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q <= {q[length-1],q[0:length-2]};
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endmodule
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endmodule
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`endif
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`endif
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`ifdef CNT_SHREG_CLEAR
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`define MODULE cnt_shreg_clear
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module `BASE`MODULE ( clear, q, rst, clk);
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`undef MODULE
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parameter length = 4;
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input clear;
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output reg [0:length-1] q;
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input rst;
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input clk;
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always @ (posedge clk or posedge rst)
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if (rst)
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q <= {1'b1,{length-1{1'b0}}};
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else
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if (clear)
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q <= {1'b1,{length-1{1'b0}}};
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else
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q <= q >> 1;
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endmodule
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`endif
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`ifdef CNT_SHREG_CE_CLEAR
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`ifdef CNT_SHREG_CE_CLEAR
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`define MODULE cnt_shreg_ce_clear
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`define MODULE cnt_shreg_ce_clear
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module `BASE`MODULE ( cke, clear, q, rst, clk);
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module `BASE`MODULE ( cke, clear, q, rst, clk);
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`undef MODULE
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`undef MODULE
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