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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Diff between revs 5 and 18

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Rev 5	Rev 18
Line 38...	Line 38...
`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`

`module cnt_shreg_wrap ( q, rst, clk);`	`module vl_cnt_shreg_wrap ( q, rst, clk);`

`parameter length = 4;`	`parameter length = 4;`
`output reg [0:length-1] q;`	`output reg [0:length-1] q;`
`input rst;`	`input rst;`
`input clk;`	`input clk;`
Line 53...	Line 53...
`else`	`else`
`q <= {q[length-1],q[0:length-2]};`	`q <= {q[length-1],q[0:length-2]};`

`endmodule`	`endmodule`

`module cnt_shreg_ce_wrap ( cke, q, rst, clk);`	`module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);`

`parameter length = 4;`	`parameter length = 4;`
`input cke;`	`input cke;`
`output reg [0:length-1] q;`	`output reg [0:length-1] q;`
`input rst;`	`input rst;`
Line 70...	Line 70...
`if (cke)`	`if (cke)`
`q <= {q[length-1],q[0:length-2]};`	`q <= {q[length-1],q[0:length-2]};`

`endmodule`	`endmodule`

`module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);`	`module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);`

`parameter length = 4;`	`parameter length = 4;`
`input cke, clear;`	`input cke, clear;`
`output reg [0:length-1] q;`	`output reg [0:length-1] q;`
`input rst;`	`input rst;`
Line 90...	Line 90...
`else`	`else`
`q <= q >> 1;`	`q <= q >> 1;`

`endmodule`	`endmodule`

`module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);`	`module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);`

`parameter length = 4;`	`parameter length = 4;`
`input cke, clear;`	`input cke, clear;`
`output reg [0:length-1] q;`	`output reg [0:length-1] q;`
`input rst;`	`input rst;`

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Diff between revs 5 and 18