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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 100 and 101

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Rev 100	Rev 101
Line 78...	Line 78...

`define WB3AVALON_BRIDGE	`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE	`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1	`define WB3_ARBITER_TYPE1
`define WB_ADR_INC	`define WB_ADR_INC
`define WB_B3_RAM_BE	`define WB_RAM
`define WB_B4_RAM_BE
`define WB_B4_ROM	`define WB_B4_ROM
`define WB_BOOT_ROM	`define WB_BOOT_ROM
`define WB_DPRAM	`define WB_DPRAM
`define WBB3_WBB4_CACHE	`define WB_CACHE

`define IO_DFF_OE	`define IO_DFF_OE
`define O_DFF	`define O_DFF

`endif	`endif
Line 111...	Line 110...
`ifndef DPRAM_BE_2R2W	`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W	`define DPRAM_BE_2R2W
`endif	`endif
`endif	`endif

`ifdef WB_B3_RAM_BE	`ifdef WB_RAM
`ifndef WB_ADR_INC	`ifndef WB_ADR_INC
`define WB_ADR_INC	`define WB_ADR_INC
`endif	`endif
`ifndef RAM_BE	`ifndef RAM_BE
`define RAM_BE	`define RAM_BE
Line 153...	Line 152...
`ifndef FIFO_2R2W_ASYNC_SIMPLEX	`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX	`define FIFO_2R2W_ASYNC_SIMPLEX
`endif	`endif
`endif	`endif

`ifdef WBB3_WBB4_CACHE	`ifdef WB_CACHE
`ifndef RAM	`ifndef RAM
`define RAM	`define RAM
`endif	`endif
`ifndef WB_ADR_INC	`ifndef WB_ADR_INC
`define WB_ADR_INC	`define WB_ADR_INC

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