URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 115 and 136

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Rev 115	Rev 136
Line 87...	Line 87...
`define WB_BOOT_ROM	`define WB_BOOT_ROM
`define WB_DPRAM	`define WB_DPRAM
`define WB_CACHE	`define WB_CACHE
`define WB_AVALON_BRIDGE	`define WB_AVALON_BRIDGE
`define WB_AVALON_MEM_CACHE	`define WB_AVALON_MEM_CACHE
	`define WB_SDR_SDRAM_CTRL

`define IO_DFF_OE	`define IO_DFF_OE
`define O_DFF	`define O_DFF
	`define O_DDR
	`define O_CLK

`endif	`endif

	`///////////////////////////////////////`
	`// dependencies`
	`///////////////////////////////////////`

`ifdef PLL	`ifdef PLL
`ifndef SYNC_RST	`ifndef SYNC_RST
`define SYNC_RST	`define SYNC_RST
`endif	`endif
`endif	`endif
Line 105...	Line 112...
`ifndef GBUF	`ifndef GBUF
`define GBUF	`define GBUF
`endif	`endif
`endif	`endif

	`ifdef WB_SDR_SDRAM_CTRL
	`ifndef WB_SHADOW_RAM
	`define WB_SHADOW_RAM
	`endif
	`ifndef WB_CACHE
	`define WB_CACHE
	`endif
	`ifndef WB_SDR_SDRAM
	`define WB_SDR_SDRAM
	`endif
	`ifndef IO_DFF_OE
	`define IO_DFF_OE
	`endif
	`ifndef O_DFF
	`define O_DFF
	`endif
	`ifndef O_CLK
	`define O_CLK
	`endif
	`endif

	`ifdef WB_SDR_SDRAM
	`ifndef CNT_SHREG_CLEAR
	`define CNT_SHREG_CLEAR
	`endif
	`ifndef CNT_LFSR_ZQ
	`define CNT_LFSR_ZQ
	`endif
	`ifndef DELAY_EMPTYFLAG
	`define DELAY_EMPTYFLAG
	`endif
	`endif

`ifdef WB_DPRAM	`ifdef WB_DPRAM
`ifndef WB_ADR_INC	`ifndef WB_ADR_INC
`define WB_ADR_INC	`define WB_ADR_INC
`endif	`endif
`ifndef DPRAM_BE_2R2W	`ifndef DPRAM_BE_2R2W
Line 179...	Line 219...
`define DPRAM_BE_2R2W	`define DPRAM_BE_2R2W
`endif	`endif
`ifndef CDC	`ifndef CDC
`define CDC	`define CDC
`endif	`endif
	`ifndef O_DFF
	`define O_DFF
	`endif
	`ifndef O_CLK
	`define O_CLK
	`endif
`endif	`endif

`ifdef WB_SHADOW_RAM	`ifdef WB_SHADOW_RAM
`ifndef WB_RAM	`ifndef WB_RAM
`define WB_RAM	`define WB_RAM
Line 319...	Line 365...
`ifndef SYNCHRONIZER	`ifndef SYNCHRONIZER
`define SYNCHRONIZER	`define SYNCHRONIZER
`endif	`endif
`endif	`endif

	`ifdef O_CLK
	`ifndef O_DDR
	`define O_DDR
	`endif
	`endif

`// size to width`	`// size to width`
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;	`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

`No newline at end of file`	`No newline at end of file`

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 115 and 136