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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 44 and 48

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Rev 44	Rev 48
Line 41...	Line 41...
`define FIFO_2R2W_SYNC_SIMPLEX	`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC	`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC	`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC	`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX	`define FIFO_2R2W_ASYNC_SIMPLEX
	`define REG_FILE

`define DFF	`define DFF
`define DFF_ARRAY	`define DFF_ARRAY
`define DFF_CE	`define DFF_CE
`define DFF_CE_CLEAR	`define DFF_CE_CLEAR
Line 58...	Line 59...
`define DELAY	`define DELAY
`define DELAY_EMPTYFLAG	`define DELAY_EMPTYFLAG

`define WB3WB3_BRIDGE	`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1	`define WB3_ARBITER_TYPE1
	`define WB_B4_ROM
`define WB_BOOT_ROM	`define WB_BOOT_ROM
`define WB_DPRAM	`define WB_DPRAM

`define IO_DFF_OE	`define IO_DFF_OE
`define O_DFF	`define O_DFF
Line 219...	Line 221...
`ifndef DFF	`ifndef DFF
`define DFF	`define DFF
`endif	`endif
`endif	`endif

`No newline at end of file`	`No newline at end of file`
	`ifdef REG_FILE
	`ifndef DPRAM_1R1W
	`define DPRAM_1R1W
	`endif
	`endif

`No newline at end of file`	`No newline at end of file`

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