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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 76 and 83

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Rev 76	Rev 83
Line 65...	Line 65...
`define DELAY_EMPTYFLAG	`define DELAY_EMPTYFLAG

`define WB3AVALON_BRIDGE	`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE	`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1	`define WB3_ARBITER_TYPE1
	`define WB_ADR_INC
`define WB_B3_RAM_BE	`define WB_B3_RAM_BE
`define WB_B4_RAM_BE	`define WB_B4_RAM_BE
`define WB_B4_ROM	`define WB_B4_ROM
`define WB_BOOT_ROM	`define WB_BOOT_ROM
`define WB_DPRAM	`define WB_DPRAM
Line 98...	Line 99...
`define SPR	`define SPR
`endif	`endif
`endif	`endif

`ifdef WB_B3_RAM_BE	`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1	`ifndef WB_ADR_INC
`define WB3_ARBITER_TYPE1	`define WB_ADR_INC
`endif	`endif
`ifndef RAM_BE	`ifndef RAM_BE
`define RAM_BE	`define RAM_BE
`endif	`endif
`endif	`endif

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