| Line 46... |
Line 46... |
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input [nr_of_ports*width-1:0] a;
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input [nr_of_ports*width-1:0] a;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output reg [width-1:0] dout;
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output reg [width-1:0] dout;
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integer i,j;
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always @ (a, sel)
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always @ (a, sel)
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begin
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begin
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dout = a[width-1:0] & {width{sel[0]}};
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dout = a[width-1:0] & {width{sel[0]}};
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for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
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for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
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dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
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for (j=0;j<32;j=j+1)
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dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
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end
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end
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endmodule
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endmodule
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module vl_mux2_andor ( a1, a0, sel, dout);
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module vl_mux2_andor ( a1, a0, sel, dout);
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| Line 64... |
Line 67... |
input [width-1:0] a1, a0;
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input [width-1:0] a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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output [width-1:0] dout;
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vl_mux_andor
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vl_mux_andor
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# ( .width(width), .nr_of_ports(nr_of_ports)
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# ( .width(width), .nr_of_ports(nr_of_ports))
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mux0( .a({a1,a0}), .sel(sel), .dout(dout));
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mux0( .a({a1,a0}), .sel(sel), .dout(dout));
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/*
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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// or
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assign dout = tmp[1] | tmp[0];
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*/
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endmodule
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endmodule
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module vl_mux3_andor ( a2, a1, a0, sel, dout);
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module vl_mux3_andor ( a2, a1, a0, sel, dout);
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parameter width = 32;
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parameter width = 32;
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| Line 88... |
Line 81... |
input [width-1:0] a2, a1, a0;
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input [width-1:0] a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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output [width-1:0] dout;
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vl_mux_andor
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vl_mux_andor
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# ( .width(width), .nr_of_ports(nr_of_ports)
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# ( .width(width), .nr_of_ports(nr_of_ports))
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mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
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mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
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/*
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[2] = {width{sel[2]}} & a2;
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// or
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assign dout = tmp[2] | tmp[1] | tmp[0];
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*/
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endmodule
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endmodule
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module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
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module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
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parameter width = 32;
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parameter width = 32;
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| Line 114... |
Line 95... |
input [width-1:0] a3, a2, a1, a0;
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input [width-1:0] a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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output [width-1:0] dout;
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vl_mux_andor
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vl_mux_andor
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# ( .width(width), .nr_of_ports(nr_of_ports)
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# ( .width(width), .nr_of_ports(nr_of_ports))
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mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
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mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
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/*
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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|
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[3] = {width{sel[3]}} & a3;
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|
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// or
|
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assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
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*/
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endmodule
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endmodule
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module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
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module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
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|
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parameter width = 32;
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parameter width = 32;
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| Line 140... |
Line 109... |
input [width-1:0] a4, a3, a2, a1, a0;
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input [width-1:0] a4, a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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output [width-1:0] dout;
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|
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vl_mux_andor
|
vl_mux_andor
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# ( .width(width), .nr_of_ports(nr_of_ports)
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# ( .width(width), .nr_of_ports(nr_of_ports))
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mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
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mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
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/*
|
|
wire [width-1:0] tmp [nr_of_ports-1:0];
|
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integer i;
|
|
|
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// and
|
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assign tmp[0] = {width{sel[0]}} & a0;
|
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assign tmp[1] = {width{sel[1]}} & a1;
|
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assign tmp[2] = {width{sel[2]}} & a2;
|
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assign tmp[3] = {width{sel[3]}} & a3;
|
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assign tmp[4] = {width{sel[4]}} & a4;
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|
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// or
|
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assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
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*/
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endmodule
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endmodule
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module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
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module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
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|
|
parameter width = 32;
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parameter width = 32;
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| Line 167... |
Line 123... |
input [width-1:0] a5, a4, a3, a2, a1, a0;
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input [width-1:0] a5, a4, a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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output [width-1:0] dout;
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|
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports)
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# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
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/*
|
|
wire [width-1:0] tmp [nr_of_ports-1:0];
|
|
integer i;
|
|
|
|
// and
|
|
assign tmp[0] = {width{sel[0]}} & a0;
|
|
assign tmp[1] = {width{sel[1]}} & a1;
|
|
assign tmp[2] = {width{sel[2]}} & a2;
|
|
assign tmp[3] = {width{sel[3]}} & a3;
|
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assign tmp[4] = {width{sel[4]}} & a4;
|
|
assign tmp[5] = {width{sel[5]}} & a5;
|
|
|
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// or
|
|
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
|
|
*/
|
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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