| Line 72... |
Line 72... |
`undef MODULE
|
`undef MODULE
|
|
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
parameter mem_size = 1<<addr_width;
|
parameter mem_size = 1<<addr_width;
|
|
parameter debug = 0;
|
input [(data_width-1):0] d;
|
input [(data_width-1):0] d;
|
input [(addr_width-1):0] adr;
|
input [(addr_width-1):0] adr;
|
input we;
|
input we;
|
output reg [(data_width-1):0] q;
|
output reg [(data_width-1):0] q;
|
input clk;
|
input clk;
|
reg [data_width-1:0] ram [mem_size-1:0];
|
reg [data_width-1:0] ram [mem_size-1:0];
|
parameter init = 0;
|
|
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate
|
|
if (memory_init == 1) begin : init_mem
|
initial
|
initial
|
begin
|
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
end else if (memory_init == 2) begin : init_zero
|
|
integer k;
|
|
initial
|
|
for (k = 0; k < mem_size; k = k + 1)
|
|
ram[k] = 0;
|
end
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (debug==1) begin : debug_we
|
|
always @ (posedge clk)
|
|
if (we)
|
|
$display ("Value %h written at address %h : time %t", d, adr, $time);
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
| Line 125... |
Line 140... |
wire [data_width/8-1:0] cke;
|
wire [data_width/8-1:0] cke;
|
//E2_endif
|
//E2_endif
|
|
|
parameter memory_init = 0;
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (memory_init) begin : init_mem
|
generate
|
|
if (memory_init == 1) begin : init_mem
|
initial
|
initial
|
begin
|
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end else if (memory_init == 2) begin : init_zero
|
|
integer k;
|
|
initial
|
|
for (k = 0; k < mem_size; k = k + 1)
|
|
ram[k] = 0;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
//E2_ifdef SYSTEMVERILOG
|
//E2_ifdef SYSTEMVERILOG
|
|
|
| Line 196... |
Line 215... |
input [(addr_width-1):0] adr_b;
|
input [(addr_width-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output [(data_width-1):0] q_b;
|
output [(data_width-1):0] q_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(addr_width-1):0] adr_b_reg;
|
reg [(addr_width-1):0] adr_b_reg;
|
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
|
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
|
|
|
parameter init = 0;
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
parameter debug = 0;
|
|
|
|
generate
|
|
if (memory_init == 1) begin : init_mem
|
initial
|
initial
|
begin
|
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
end else if (memory_init == 2) begin : init_zero
|
|
integer k;
|
|
initial
|
|
for (k = 0; k < mem_size; k = k + 1)
|
|
ram[k] = 0;
|
end
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (debug==1) begin : debug_we
|
|
always @ (posedge clk_a)
|
|
if (we_a)
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
if (we_a)
|
if (we_a)
|
| Line 236... |
Line 270... |
output reg [(data_width-1):0] q_a;
|
output reg [(data_width-1):0] q_a;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(data_width-1):0] q_b;
|
reg [(data_width-1):0] q_b;
|
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
|
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
|
|
|
parameter init = 0;
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
parameter debug = 0;
|
|
|
|
generate
|
|
if (memory_init == 1) begin : init_mem
|
initial
|
initial
|
begin
|
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
end else if (memory_init == 2) begin : init_zero
|
|
integer k;
|
|
initial
|
|
for (k = 0; k < mem_size; k = k + 1)
|
|
ram[k] = 0;
|
end
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (debug==1) begin : debug_we
|
|
always @ (posedge clk_a)
|
|
if (we_a)
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
begin
|
begin
|
| Line 257... |
Line 306... |
always @ (posedge clk_b)
|
always @ (posedge clk_b)
|
q_b <= ram[adr_b];
|
q_b <= ram[adr_b];
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
|
`ifdef DPRAM_1R2W
|
|
`define MODULE dpram_1r2w
|
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
|
|
`undef MODULE
|
|
|
|
parameter data_width = 32;
|
|
parameter addr_width = 8;
|
|
parameter mem_size = 1<<addr_width;
|
|
input [(data_width-1):0] d_a;
|
|
input [(addr_width-1):0] adr_a;
|
|
input [(addr_width-1):0] adr_b;
|
|
input we_a;
|
|
input [(data_width-1):0] d_b;
|
|
output reg [(data_width-1):0] q_a;
|
|
input we_b;
|
|
input clk_a, clk_b;
|
|
reg [(data_width-1):0] q_b;
|
|
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
|
|
|
|
parameter memory_init = 0;
|
|
parameter memory_file = "vl_ram.vmem";
|
|
parameter debug = 0;
|
|
|
|
generate
|
|
if (memory_init == 1) begin : init_mem
|
|
initial
|
|
$readmemh(memory_file, ram);
|
|
end else if (memory_init == 2) begin : init_zero
|
|
integer k;
|
|
initial
|
|
for (k = 0; k < mem_size; k = k + 1)
|
|
ram[k] = 0;
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (debug==1) begin : debug_we
|
|
always @ (posedge clk_a)
|
|
if (we_a)
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
|
always @ (posedge clk_b)
|
|
if (we_b)
|
|
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
|
|
end
|
|
endgenerate
|
|
|
|
always @ (posedge clk_a)
|
|
begin
|
|
q_a <= ram[adr_a];
|
|
if (we_a)
|
|
ram[adr_a] <= d_a;
|
|
end
|
|
always @ (posedge clk_b)
|
|
begin
|
|
if (we_b)
|
|
ram[adr_b] <= d_b;
|
|
end
|
|
endmodule
|
|
`endif
|
|
|
`ifdef DPRAM_2R2W
|
`ifdef DPRAM_2R2W
|
`define MODULE dpram_2r2w
|
`define MODULE dpram_2r2w
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
|
`undef MODULE
|
`undef MODULE
|
|
|
| Line 277... |
Line 386... |
input we_b;
|
input we_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(data_width-1):0] q_b;
|
reg [(data_width-1):0] q_b;
|
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
|
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
|
|
|
parameter init = 0;
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
parameter debug = 0;
|
|
|
|
generate
|
|
if (memory_init) begin : init_mem
|
initial
|
initial
|
begin
|
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
end else if (memory_init == 2) begin : init_zero
|
|
integer k;
|
|
initial
|
|
for (k = 0; k < mem_size; k = k + 1)
|
|
ram[k] = 0;
|
end
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (debug==1) begin : debug_we
|
|
always @ (posedge clk_a)
|
|
if (we_a)
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
|
always @ (posedge clk_b)
|
|
if (we_b)
|
|
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge clk_a)
|
always @ (posedge clk_a)
|
begin
|
begin
|
| Line 315... |
Line 441... |
parameter b_data_width = 64; //a_data_width;
|
parameter b_data_width = 64; //a_data_width;
|
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
|
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
|
localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
|
localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
|
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
|
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
|
|
|
parameter init = 0;
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
|
parameter debug = 0;
|
|
|
input [(a_data_width-1):0] d_a;
|
input [(a_data_width-1):0] d_a;
|
input [(a_addr_width-1):0] adr_a;
|
input [(a_addr_width-1):0] adr_a;
|
input [(a_data_width/8-1):0] be_a;
|
input [(a_data_width/8-1):0] be_a;
|
input we_a;
|
input we_a;
|
| Line 330... |
Line 457... |
input [(b_data_width/8-1):0] be_b;
|
input [(b_data_width/8-1):0] be_b;
|
input we_b;
|
input we_b;
|
output reg [(b_data_width-1):0] q_b;
|
output reg [(b_data_width-1):0] q_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
|
|
|
generate
|
|
if (debug==1) begin : debug_we
|
|
always @ (posedge clk_a)
|
|
if (we_a)
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
|
always @ (posedge clk_b)
|
|
if (we_b)
|
|
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
|
|
end
|
|
endgenerate
|
|
|
|
|
//E2_ifdef SYSTEMVERILOG
|
//E2_ifdef SYSTEMVERILOG
|
// use a multi-dimensional packed array
|
// use a multi-dimensional packed array
|
//to model individual bytes within the word
|
//to model individual bytes within the word
|
|
|
generate
|
generate
|
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
|
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
|
|
|
logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
|
|
initial
|
initial
|
if (init)
|
if (memory_init==1)
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
|
|
integer k;
|
|
initial
|
|
if (memory_init==2)
|
|
for (k = 0; k < mem_size; k = k + 1)
|
|
ram[k] = 0;
|
|
|
always_ff@(posedge clk_a)
|
always_ff@(posedge clk_a)
|
begin
|
begin
|
if(we_a) begin
|
if(we_a) begin
|
if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
|
if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
|
if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
|
if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
|
if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
|
if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
|
if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
|
if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
|
end
|
end
|
end
|
end
|
|
|
always@(posedge clk_a)
|
always@(posedge clk_a)
|
q_a = ram[adr_a];
|
q_a = ram[adr_a];
|
|
|
always_ff@(posedge clk_b)
|
always_ff@(posedge clk_b)
|
begin
|
begin
|
if(we_b) begin
|
if(we_b) begin
|
if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
|
if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
|
if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
|
if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
|
if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
|
if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
|
if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
|
if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
|
end
|
end
|
end
|
end
|
|
|
always@(posedge clk_b)
|
always@(posedge clk_b)
|
q_b = ram[adr_b];
|
q_b = ram[adr_b];
|
| Line 378... |
Line 523... |
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
|
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
|
|
|
logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
|
|
initial
|
initial
|
if (init)
|
if (memory_init==1)
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
|
|
integer k;
|
|
initial
|
|
if (memory_init==2)
|
|
for (k = 0; k < mem_size; k = k + 1)
|
|
ram[k] = 0;
|
|
|
always_ff@(posedge clk_a)
|
always_ff@(posedge clk_a)
|
begin
|
begin
|
if(we_a) begin
|
if(we_a) begin
|
if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
|
if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
|
if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
|
if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
|
| Line 422... |
Line 573... |
|
|
generate
|
generate
|
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
|
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
|
logic [31:0] temp;
|
logic [31:0] temp;
|
`define MODULE dpram_be_2r2w
|
`define MODULE dpram_be_2r2w
|
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
|
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
|
`undef MODULE
|
`undef MODULE
|
dpram6464 (
|
dpram6464 (
|
.d_a(d_a),
|
.d_a(d_a),
|
.q_a(q_a),
|
.q_a(q_a),
|
.adr_a(adr_a),
|
.adr_a(adr_a),
|
| Line 439... |
Line 590... |
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
|
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
|
.we_b(we_b),
|
.we_b(we_b),
|
.clk_b(clk_b)
|
.clk_b(clk_b)
|
);
|
);
|
|
|
always_comb
|
always @ (adr_b[0] or temp)
|
if (adr_b[0])
|
if (adr_b[0])
|
q_b = temp[31:16];
|
q_b = temp[31:16];
|
else
|
else
|
q_b = temp[15:0];
|
q_b = temp[15:0];
|
|
|
| Line 452... |
Line 603... |
|
|
generate
|
generate
|
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
|
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
|
logic [63:0] temp;
|
logic [63:0] temp;
|
`define MODULE dpram_be_2r2w
|
`define MODULE dpram_be_2r2w
|
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
|
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
|
`undef MODULE
|
`undef MODULE
|
dpram6464 (
|
dpram6464 (
|
.d_a({d_a,d_a}),
|
.d_a({d_a,d_a}),
|
.q_a(temp),
|
.q_a(temp),
|
.adr_a(adr_a[a_addr_width-1:1]),
|
.adr_a(adr_a[a_addr_width-1:1]),
|
| Line 469... |
Line 620... |
.be_b(be_b),
|
.be_b(be_b),
|
.we_b(we_b),
|
.we_b(we_b),
|
.clk_b(clk_b)
|
.clk_b(clk_b)
|
);
|
);
|
|
|
always_comb
|
always @ (adr_a[0] or temp)
|
if (adr_a[0])
|
if (adr_a[0])
|
q_a = temp[63:32];
|
q_a = temp[63:32];
|
else
|
else
|
q_a = temp[31:0];
|
q_a = temp[31:0];
|
|
|
