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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 128 and 137

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Rev 128 Rev 137
Line 597... Line 597... 
    .we_a(we_a),
 
    .we_a(we_a),
 
    .clk_a(clk_a),
 
    .clk_a(clk_a),
 
    .d_b({d_b,d_b}),
 
    .d_b({d_b,d_b}),
 
    .q_b(temp),
 
    .q_b(temp),
 
    .adr_b(adr_b[b_addr_width-1:1]),
 
    .adr_b(adr_b[b_addr_width-1:1]),
 
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
 
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
 
    .we_b(we_b),
 
    .we_b(we_b),
 
    .clk_b(clk_b)
 
    .clk_b(clk_b)
 
);
 
);
 
 
 
 
 
always @ (adr_b[0] or temp)
 
always @ (adr_b[0] or temp)

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