| Line 58... |
Line 58... |
always @ (posedge clk)
|
always @ (posedge clk)
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q <= rom[adr];
|
q <= rom[adr];
|
|
|
endmodule
|
endmodule
|
|
|
module vl_rom ( adr, q, clk);
|
/*
|
|
module vl_rom ( adr, q, clk);
|
parameter data_width = 32;
|
|
parameter addr_width = 4;
|
|
|
|
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
|
parameter data_width = 32;
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{32'h18000000},
|
parameter addr_width = 4;
|
{32'hA8200000},
|
|
{32'hA8200000},
|
|
{32'hA8200000},
|
|
{32'h44003000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000}};
|
|
|
|
input [addr_width-1:0] adr;
|
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
|
output reg [data_width-1:0] q;
|
{32'h18000000},
|
input clk;
|
{32'hA8200000},
|
|
{32'hA8200000},
|
|
{32'hA8200000},
|
|
{32'h44003000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000}};
|
|
|
|
input [addr_width-1:0] adr;
|
|
output reg [data_width-1:0] q;
|
|
input clk;
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
q <= data[adr];
|
q <= data[adr];
|
|
|
endmodule
|
|
|
|
|
endmodule
|
|
*/
|
// Single port RAM
|
// Single port RAM
|
|
|
module vl_ram ( d, adr, we, q, clk);
|
module vl_ram ( d, adr, we, q, clk);
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
| Line 285... |
Line 286... |
|
|
parameter going_empty = 1'b0;
|
parameter going_empty = 1'b0;
|
parameter going_full = 1'b1;
|
parameter going_full = 1'b1;
|
|
|
input [N:0] wptr, rptr;
|
input [N:0] wptr, rptr;
|
output reg fifo_empty;
|
output fifo_empty;
|
output fifo_full;
|
output fifo_full;
|
input wclk, rclk, rst;
|
input wclk, rclk, rst;
|
|
|
`ifndef GENERATE_DIRECTION_AS_LATCH
|
`ifndef GENERATE_DIRECTION_AS_LATCH
|
wire direction;
|
wire direction;
|
| Line 299... |
Line 300... |
`endif
|
`endif
|
reg direction_set, direction_clr;
|
reg direction_set, direction_clr;
|
|
|
wire async_empty, async_full;
|
wire async_empty, async_full;
|
wire fifo_full2;
|
wire fifo_full2;
|
reg fifo_empty2;
|
wire fifo_empty2;
|
|
|
// direction_set
|
// direction_set
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
{Q1,Q2} : direction_set <= 1'b1;
|
{Q1,Q2} : direction_set <= 1'b1;
|
| Line 351... |
Line 352... |
else if (async_full)
|
else if (async_full)
|
{fifo_full, fifo_full2} <= 2'b11;
|
{fifo_full, fifo_full2} <= 2'b11;
|
else
|
else
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
*/
|
*/
|
always @ (posedge rclk or posedge async_empty)
|
/* always @ (posedge rclk or posedge async_empty)
|
if (async_empty)
|
if (async_empty)
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
else
|
else
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
|
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
|
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
|
|
endmodule // async_comp
|
endmodule // async_comp
|
|
|
module vl_fifo_1r1w_async (
|
module vl_fifo_1r1w_async (
|
d, wr, fifo_full, wr_clk, wr_rst,
|
d, wr, fifo_full, wr_clk, wr_rst,
|
