URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 28 and 31

Rev 28	Rev 31
Line 307...	Line 307...

`vl_dpram_1r1w`	`vl_dpram_1r1w`
`# (.data_width(data_width), .addr_width(addr_width))`	`# (.data_width(data_width), .addr_width(addr_width))`
`dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));`	`dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));`

`vl_cnt_bin_ce_rew_zq_l1`	`vl_cnt_bin_ce_rew_q_zq_l1`
`# (.length(addr_width+1), .level1_value(1<<addr_width))`	`# (.length(addr_width+1), .level1_value(1<<addr_width))`
`fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));`	`fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));`

`endmodule`	`endmodule`