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        // ACTEL FPGA should not use logic to handle rw collision

`ifdef REG_FILE

`define MODULE reg_file

module `BASE`MODULE (

`undef MODULE

    a1, a2, a3, wd3, we3, rd1, rd2, clk

);

parameter data_width = 32;

parameter addr_width = 5;

input [addr_width-1:0] a1, a2, a3;

input [data_width-1:0] wd3;

input we3;

output [data_width-1:0] rd1, rd2;

input clk;

`ifdef ACTEL

reg [data_width-1:0] wd3_reg;

reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;

reg we3_reg;

reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;

reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;

always @ (posedge clk or posedge rst)

if (rst)

    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};

else

    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};

    always @ (negedge clk)

    if (we3_reg)

        ram1[a3_reg] <= wd3;

    always @ (posedge clk)

        a1_reg <= a1;

    assign rd1 = ram1[a1_reg];

    always @ (negedge clk)

    if (we3_reg)

        ram2[a3_reg] <= wd3;

    always @ (posedge clk)

        a2_reg <= a2;

    assign rd2 = ram2[a2_reg];

`else

`define MODULE dpram_1r1w

`BASE`MODULE

    # ( .data_width(data_width), .addr_width(addr_width))

    ram1 (

        .d_a(wd3),

        .adr_a(a3),

        .we_a(we3),

        .clk_a(clk),

        .q_b(rd1),

        .adr_b(a1),

        .clk_b(clk) );

`BASE`MODULE

    # ( .data_width(data_width), .addr_width(addr_width))

    ram2 (

        .d_a(wd3),

        .adr_a(a3),

        .we_a(we3),

        .clk_a(clk),

        .q_b(rd2),

        .adr_b(a2),

        .clk_b(clk) );

`undef MODULE

`endif

endmodule

`endif