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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 72 and 73

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Rev 72 Rev 73
Line 106... Line 106... 
   parameter data_width = 32;
 
   parameter data_width = 32;
 
   parameter addr_width = 6;
 
   parameter addr_width = 6;
 
   parameter mem_size = 256;
 
   parameter mem_size = 256;
 
   input [(data_width-1):0]      d;
 
   input [(data_width-1):0]      d;
 
   input [(addr_width-1):0]       adr;
 
   input [(addr_width-1):0]       adr;
 
   input [(addr_width/4)-1:0]    be;
 
   input [(data_width/8)-1:0]    be;
 
   input                         we;
 
   input                         we;
 
   output reg [(data_width-1):0] q;
 
   output reg [(data_width-1):0] q;
 
   input                         clk;
 
   input                         clk;
 
 
 
 
 
//E2_ifdef SYSTEMVERILOG
 
//E2_ifdef SYSTEMVERILOG

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