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direction <= going_empty;
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direction <= going_empty;
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else
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else
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direction <= going_full;*/
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direction <= going_full;*/
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endmodule
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endmodule
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`endif
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`endif
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module delay ( d, q, clk, rst);
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parameter depth = 10;
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input d;
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output q;
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input clk, rst;
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reg [1:depth] dffs;
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always @ (posedge clk or posedge rst)
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if (rst)
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dffs <= {depth{1'b0}};
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else
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dffs <= {d,dffs[1:depth-1]};
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assign q = dffs[depth];
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endmodule
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