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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 17 and 18

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Rev 17 Rev 18
Line 38... Line 38... 
//// Public License along with this source; if not, download it   ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
 
 
 
 
module dff ( d, q, clk, rst);
 
module vl_dff ( d, q, clk, rst);
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        parameter reset_value = 0;
 
 
 
 
 
        input [width-1:0] d;
 
        input [width-1:0] d;
Line 55... Line 55... 
        else
 
        else
 
                q <= d;
 
                q <= d;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
module dff_array ( d, q, clk, rst);
 
module vl_dff_array ( d, q, clk, rst);
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter depth = 2;
 
        parameter depth = 2;
 
        parameter reset_value = 1'b0;
 
        parameter reset_value = 1'b0;
 
 
 
 
Line 80... Line 80... 
 
 
 
 
    assign q = q_tmp[depth-1];
 
    assign q = q_tmp[depth-1];
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
module dff_ce ( d, ce, q, clk, rst);
 
module vl_dff_ce ( d, ce, q, clk, rst);
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        parameter reset_value = 0;
 
 
 
 
 
        input [width-1:0] d;
 
        input [width-1:0] d;
Line 98... Line 98... 
                if (ce)
 
                if (ce)
 
                        q <= d;
 
                        q <= d;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
module dff_ce_clear ( d, ce, clear, q, clk, rst);
 
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        parameter reset_value = 0;
 
 
 
 
 
        input [width-1:0] d;
 
        input [width-1:0] d;
Line 158... Line 158... 
 
 
 
 
 
 
 
 
// synopsys translate_off
 
// synopsys translate_off
 
`timescale 1 ps / 1 ps
 
`timescale 1 ps / 1 ps
 
// synopsys translate_on
 
// synopsys translate_on
 
module dff_sr (
 
module vl_dff_sr (
 
        aclr,
 
        aclr,
 
        aset,
 
        aset,
 
        clock,
 
        clock,
 
        data,
 
        data,
 
        q);
 
        q);
Line 243... Line 243... 
 
 
 
 
 
 
 
 
`else
 
`else
 
 
 
 
 
 
 
 
 
module dff_sr ( aclr, aset, clock, data, q);
 
module vl_dff_sr ( aclr, aset, clock, data, q);
 
 
 
 
 
    input         aclr;
 
    input         aclr;
 
    input         aset;
 
    input         aset;
 
    input         clock;
 
    input         clock;
 
    input         data;
 
    input         data;
Line 266... Line 266... 
`endif
 
`endif
 
 
 
 
 
// LATCH
 
// LATCH
 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
 
`ifdef ALTERA
 
`ifdef ALTERA
 
module latch ( d, le, q, clk);
 
module vl_latch ( d, le, q, clk);
 
input d, le;
 
input d, le;
 
output q;
 
output q;
 
input clk;
 
input clk;
 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
 
endmodule
 
endmodule
Line 285... Line 285... 
     else
 
     else
 
       direction <= going_full;*/
 
       direction <= going_full;*/
 
endmodule
 
endmodule
 
`endif
 
`endif
 
 
 
 
 
module shreg ( d, q, clk, rst);
 
module vl_shreg ( d, q, clk, rst);
 
parameter depth = 10;
 
parameter depth = 10;
 
input d;
 
input d;
 
output q;
 
output q;
 
input clk, rst;
 
input clk, rst;
 
 
 
 
Line 301... Line 301... 
else
 
else
 
    dffs <= {d,dffs[1:depth-1]};
 
    dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
assign q = dffs[depth];
 
endmodule
 
endmodule
 
 
 
 
 
module shreg_ce ( d, ce, q, clk, rst);
 
module vl_shreg_ce ( d, ce, q, clk, rst);
 
parameter depth = 10;
 
parameter depth = 10;
 
input d, ce;
 
input d, ce;
 
output q;
 
output q;
 
input clk, rst;
 
input clk, rst;
 
 
 
 
Line 318... Line 318... 
    if (ce)
 
    if (ce)
 
        dffs <= {d,dffs[1:depth-1]};
 
        dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
assign q = dffs[depth];
 
endmodule
 
endmodule
 
 
 
 
 
module delay ( d, q, clk, rst);
 
module vl_delay ( d, q, clk, rst);
 
parameter depth = 10;
 
parameter depth = 10;
 
input d;
 
input d;
 
output q;
 
output q;
 
input clk, rst;
 
input clk, rst;
 
 
 
 
Line 334... Line 334... 
else
 
else
 
    dffs <= {d,dffs[1:depth-1]};
 
    dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
assign q = dffs[depth];
 
endmodule
 
endmodule
 
 
 
 
 
module delay_emptyflag ( d, q, emptyflag, clk, rst);
 
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
 
parameter depth = 10;
 
parameter depth = 10;
 
input d;
 
input d;
 
output q, emptyflag;
 
output q, emptyflag;
 
input clk, rst;
 
input clk, rst;
 
 
 
 

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