| Line 6025... |
Line 6025... |
assign wb_ack_o = wb_ack;
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assign wb_ack_o = wb_ack;
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|
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endmodule
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endmodule
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`endif
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`endif
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`ifdef WB_B3_DPRAM
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`ifdef WB_DPRAM
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`define MODULE wb_b3_dpram
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`define MODULE wb_dpram
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module `BASE`MODULE (
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module `BASE`MODULE (
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`undef MODULE
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`undef MODULE
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// wishbone slave side a
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// wishbone slave side a
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wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
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wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
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wbsa_clk, wbsa_rst,
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wbsa_clk, wbsa_rst,
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// wishbone slave side b
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// wishbone slave side b
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wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
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wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
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wbsb_clk, wbsb_rst);
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wbsb_clk, wbsb_rst);
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|
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parameter data_width_a = 32;
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parameter data_width_a = 32;
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parameter data_width_b = data_width_a;
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parameter data_width_b = data_width_a;
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parameter addr_width_a = 8;
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parameter addr_width_a = 8;
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| Line 6052... |
Line 6052... |
input [2:0] wbsa_cti_i;
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input [2:0] wbsa_cti_i;
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input [1:0] wbsa_bte_i;
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input [1:0] wbsa_bte_i;
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input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
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input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
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output [data_width_a-1:0] wbsa_dat_o;
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output [data_width_a-1:0] wbsa_dat_o;
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output wbsa_ack_o;
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output wbsa_ack_o;
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output wbsa_stall_o;
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input wbsa_clk, wbsa_rst;
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input wbsa_clk, wbsa_rst;
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|
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input [data_width_b-1:0] wbsb_dat_i;
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input [data_width_b-1:0] wbsb_dat_i;
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input [addr_width_b-1:0] wbsb_adr_i;
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input [addr_width_b-1:0] wbsb_adr_i;
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input [data_width_b/8-1:0] wbsb_sel_i;
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input [data_width_b/8-1:0] wbsb_sel_i;
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input [2:0] wbsb_cti_i;
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input [2:0] wbsb_cti_i;
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input [1:0] wbsb_bte_i;
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input [1:0] wbsb_bte_i;
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input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
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input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
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output [data_width_b-1:0] wbsb_dat_o;
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output [data_width_b-1:0] wbsb_dat_o;
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output wbsb_ack_o;
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output wbsb_ack_o;
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output wbsb_stall_o;
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input wbsb_clk, wbsb_rst;
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input wbsb_clk, wbsb_rst;
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|
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wire [addr_width_a-1:0] adr_a;
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wire [addr_width_a-1:0] adr_a;
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wire [addr_width_b-1:0] adr_b;
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wire [addr_width_b-1:0] adr_b;
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wire we_a, we_b;
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wire we_a, we_b;
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