| Line 4348... |
Line 4348... |
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generate
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generate
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if (a_data_width==32 & b_data_width==16) begin : dpram_3216
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if (a_data_width==32 & b_data_width==16) begin : dpram_3216
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logic [31:0] temp;
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logic [31:0] temp;
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`define MODULE dpram_be_2r2w
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`define MODULE dpram_be_2r2w
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`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
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`BASE`MODULE # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
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`undef MODULE
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`undef MODULE
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dpram6464 (
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dpram3232 (
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.d_a(d_a),
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.d_a(d_a),
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.q_a(q_a),
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.q_a(q_a),
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.adr_a(adr_a),
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.adr_a(adr_a),
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.be_a(be_a),
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.be_a(be_a),
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.we_a(we_a),
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.we_a(we_a),
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.clk_a(clk_a),
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.clk_a(clk_a),
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.d_b({d_b,d_b}),
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.d_b({d_b,d_b}),
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.q_b(temp),
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.q_b(temp),
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.adr_b(adr_b),
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.adr_b(adr_b[b_addr_width-1:1]),
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.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
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.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
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.we_b(we_b),
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.we_b(we_b),
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.clk_b(clk_b)
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.clk_b(clk_b)
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);
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);
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|
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| Line 4378... |
Line 4378... |
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generate
|
generate
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if (a_data_width==32 & b_data_width==64) begin : dpram_3264
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if (a_data_width==32 & b_data_width==64) begin : dpram_3264
|
logic [63:0] temp;
|
logic [63:0] temp;
|
`define MODULE dpram_be_2r2w
|
`define MODULE dpram_be_2r2w
|
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
|
`BASE`MODULE # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
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`undef MODULE
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`undef MODULE
|
dpram6464 (
|
dpram6464 (
|
.d_a({d_a,d_a}),
|
.d_a({d_a,d_a}),
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.q_a(temp),
|
.q_a(temp),
|
.adr_a(adr_a[a_addr_width-1:1]),
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.adr_a(adr_a[a_addr_width-1:1]),
|
