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Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 41 and 42

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Rev 41	Rev 42
Line 80...	Line 80...
`define SPR	`define SPR
`endif	`endif
`endif	`endif

`ifdef WB3_ARBITER_TYPE1	`ifdef WB3_ARBITER_TYPE1
	`ifndef SPR
	`define SPR
	`endif
`ifndef MUX_ANDOR	`ifndef MUX_ANDOR
`define MUX_ANDOR	`define MUX_ANDOR
`endif	`endif
`endif	`endif

Line 1164...	Line 1167...
`integer i,j;`	`integer i,j;`

`always @ (a, sel)`	`always @ (a, sel)`
`begin`	`begin`
`dout = a[width-1:0] & {width{sel[0]}};`	`dout = a[width-1:0] & {width{sel[0]}};`
`for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)`	`for (i=1;i<nr_of_ports;i=i+1)`
`for (j=0;j<32;j=j+1)`	`for (j=0;j<width;j=j+1)`
`dout[j] = (a[(i-1)*width + j] & sel[i]) \| dout[j];`	`dout[j] = (a[i*width + j] & sel[i]) \| dout[j];`
`end`	`end`

`endmodule`	`endmodule`
`endif	`endif

Line 4189...	Line 4192...
`undef MODULE	`undef MODULE

`assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;`	`assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;`

`define MODULE cnt_shreg_ce_clear	`define MODULE cnt_shreg_ce_clear
`vl_cnt_shreg_ce_clear # ( .length(16))`	`BASE`MODULE # ( .length(16))
`undef MODULE	`undef MODULE
`cnt1 (`	`cnt1 (`
`.cke(wbm_ack_i),`	`.cke(wbm_ack_i),`
`.clear(wbm_eoc),`	`.clear(wbm_eoc),`
`.q(wbm_count),`	`.q(wbm_count),`
Line 4245...	Line 4248...
`undef CTI	`undef CTI
`endif	`endif

`ifdef WB3_ARBITER_TYPE1	`ifdef WB3_ARBITER_TYPE1
`define MODULE wb3_arbiter_type1	`define MODULE wb3_arbiter_type1
`module vl_wb3_arbiter_type1 (`	module `BASE`MODULE (
`undef MODULE	`undef MODULE
`wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,`	`wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,`
`wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,`	`wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,`
`wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,`	`wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,`
`wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,`	`wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,`
Line 4327...	Line 4330...
`end`	`end`
`endgenerate`	`endgenerate`

`generate`	`generate`
`for (i=0;i<nr_of_ports;i=i+1) begin`	`for (i=0;i<nr_of_ports;i=i+1) begin`
`vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));`	`define MODULE spr
	`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
	`undef MODULE
`end`	`end`
`endgenerate`	`endgenerate`

`assign sel = select \| state;`	`assign sel = select \| state;`

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 41 and 42