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| Rev 64 |
Rev 65 |
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Line 3529... |
input [(addr_width/4)-1:0] be;
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input [(addr_width/4)-1:0] be;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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`ifdef SYSTEMVERILOG
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logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
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`else
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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`endif
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (memory_init) begin : init_mem
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generate if (memory_init) begin : init_mem
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initial
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initial
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| Line 3545... |
Line 3549... |
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`ifdef SYSTEMVERILOG
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`ifdef SYSTEMVERILOG
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// use a multi-dimensional packed array
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// use a multi-dimensional packed array
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//to model individual bytes within the word
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//to model individual bytes within the word
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logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width
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always_ff@(posedge clk)
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always_ff@(posedge clk)
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begin
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begin
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if(we) begin // note: we should have a for statement to support any bus width
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if(we) begin // note: we should have a for statement to support any bus width
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if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24];
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if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
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if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16];
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if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
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if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8];
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if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
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if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0];
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if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
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end
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end
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q <= ram[raddr];
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q <= ram[adr];
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end
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end
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`else
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`else
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genvar i;
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genvar i;
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