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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 7 and 8

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Rev 7	Rev 8
Line 342...	Line 342...
`if (ce)`	`if (ce)`
`q <= d;`	`q <= d;`

`endmodule`	`endmodule`

	`module dff_ce_clear ( d, ce, clear, q, clk, rst);`

	`parameter width = 1;`
	`parameter reset_value = 0;`

	`input [width-1:0] d;`
	`input ce, clk, rst;`
	`output reg [width-1:0] q;`

	`always @ (posedge clk or posedge rst)`
	`if (rst)`
	`q <= reset_value;`
	`else`
	`if (ce)`
	`if (clear)`
	`q <= {width{1'b0}};`
	`else`
	`q <= d;`

	`endmodule`

`ifdef ALTERA	`ifdef ALTERA
`// megafunction wizard: %LPM_FF%`	`// megafunction wizard: %LPM_FF%`
`// GENERATION: STANDARD`	`// GENERATION: STANDARD`
`// VERSION: WM1.0`	`// VERSION: WM1.0`
`// MODULE: lpm_ff`	`// MODULE: lpm_ff`
Line 1966...	Line 1987...
`# (.addr_width(addr_width))`	`# (.addr_width(addr_width))`
`cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );`	`cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );`

`endmodule`	`endmodule`

`module vl_fifo_2r2w (`	`module vl_fifo_2r2w_async (`
`// a side`	`// a side`
`a_d, a_wr, a_fifo_full,`	`a_d, a_wr, a_fifo_full,`
`a_q, a_rd, a_fifo_empty,`	`a_q, a_rd, a_fifo_empty,`
`a_clk, a_rst,`	`a_clk, a_rst,`
`// b side`	`// b side`
Line 2014...	Line 2035...
`.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)`	`.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)`
`);`	`);`

`endmodule`	`endmodule`

`module vl_fifo_2r2w_simplex (`	`module vl_fifo_2r2w_async_simplex (`
`// a side`	`// a side`
`a_d, a_wr, a_fifo_full,`	`a_d, a_wr, a_fifo_full,`
`a_q, a_rd, a_fifo_empty,`	`a_q, a_rd, a_fifo_empty,`
`a_clk, a_rst,`	`a_clk, a_rst,`
`// b side`	`// b side`

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 7 and 8