| Line 2969... |
Line 2969... |
end else if (wbs_mode=="B4") begin : inst_b4
|
end else if (wbs_mode=="B4") begin : inst_b4
|
end
|
end
|
endgenerate
|
endgenerate
|
localparam cache_mem_b_aw =
|
localparam cache_mem_b_aw =
|
(dw_s==dw_m) ? aw_slot+aw_offset :
|
(dw_s==dw_m) ? aw_slot+aw_offset :
|
(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
|
(dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
|
(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
|
(dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
|
(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
|
(dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
|
(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
|
(dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
|
(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
|
(dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
|
(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
|
(dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
|
(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
|
(dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
|
(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
|
(dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
|
vl_dpram_be_2r2w
|
vl_dpram_be_2r2w
|
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
|
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
.d_b(wbm_dat_i), .adr_b(wbm_adr_o[cache_mem_b_aw-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
.d_b(wbm_dat_i), .adr_b(wbm_adr_o[cache_mem_b_aw-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
