Line 1871... |
Line 1871... |
.we_a(we_a),
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.we_a(we_a),
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.clk_a(clk_a),
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.clk_a(clk_a),
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.d_b({d_b,d_b}),
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.d_b({d_b,d_b}),
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.q_b(temp),
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.q_b(temp),
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.adr_b(adr_b[b_addr_width-1:1]),
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.adr_b(adr_b[b_addr_width-1:1]),
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.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
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.be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
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.we_b(we_b),
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.we_b(we_b),
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.clk_b(clk_b)
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.clk_b(clk_b)
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);
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);
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always @ (adr_b[0] or temp)
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always @ (adr_b[0] or temp)
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if (adr_b[0])
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if (adr_b[0])
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Line 3062... |
Line 3062... |
// cdc
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// cdc
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wire done, mem_alert, mem_done;
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wire done, mem_alert, mem_done;
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// wbm side
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// wbm side
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reg [aw_m-1:0] wbm_radr;
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reg [aw_m-1:0] wbm_radr;
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reg [aw_m-1:0] wbm_wadr;
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reg [aw_m-1:0] wbm_wadr;
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wire [aw_slot-1:0] wbm_adr;
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//wire [aw_slot-1:0] wbm_adr;
|
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wire [aw_m-1:0] wbm_adr;
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wire wbm_radr_cke, wbm_wadr_cke;
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wire wbm_radr_cke, wbm_wadr_cke;
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reg [2:0] phase;
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reg [2:0] phase;
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// phase = {we,stb,cyc}
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// phase = {we,stb,cyc}
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localparam wbm_wait = 3'b000;
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localparam wbm_wait = 3'b000;
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localparam wbm_wr = 3'b111;
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localparam wbm_wr = 3'b111;
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Line 3234... |
Line 3235... |
endcase
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endcase
|
end
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end
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endgenerate
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endgenerate
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assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
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assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
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assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
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assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
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assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
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assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
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assign wbm_sel_o = {dw_m/8{1'b1}};
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assign wbm_sel_o = {dw_m/8{1'b1}};
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assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
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assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
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assign wbm_bte_o = bte;
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assign wbm_bte_o = bte;
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assign {wbm_we_o, wbm_stb_o, wbm_cyc_o} = phase;
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assign {wbm_we_o, wbm_stb_o, wbm_cyc_o} = phase;
|
endmodule
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endmodule
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