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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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input clk;
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input clk;
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generate
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generate
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if (debug==1) begin : debug_we
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if (debug==1) begin : debug_we
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always @ (posedge clk)
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always @ (posedge clk)
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if (we3)
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if (we3)
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$display ("Value %h written at register %h : time %t", d, adr, $time);
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$display ("Value %h written at register %h : time %t", wd3, a3, $time);
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end
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end
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endgenerate
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endgenerate
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reg [data_width-1:0] wd3_reg;
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reg [data_width-1:0] wd3_reg;
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reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
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reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
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reg we3_reg;
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reg we3_reg;
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