| Line 3394... |
Line 3394... |
vl_fifo_cmp_async
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vl_fifo_cmp_async
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# (.addr_width(addr_width))
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# (.addr_width(addr_width))
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cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
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cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
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endmodule
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endmodule
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module vl_reg_file (
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module vl_reg_file (
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a1, a2, a3, wd3, we3, rd1, rd2, clk
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a1, a2, a3, wd3, we3, rd1, rd2, clk, rst );
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);
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parameter dw = 32;
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parameter data_width = 32;
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parameter aw = 5;
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parameter addr_width = 5;
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parameter debug = 0;
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parameter debug = 0;
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input [addr_width-1:0] a1, a2, a3;
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input [aw-1:0] a1, a2, a3;
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input [data_width-1:0] wd3;
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input [dw-1:0] wd3;
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input we3;
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input we3;
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output [data_width-1:0] rd1, rd2;
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output [dw-1:0] rd1, rd2;
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input clk;
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input clk;
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wire [dw-1:0] rd1mem, rd2mem;
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reg [dw-1:0] wreg;
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reg sel1, sel2;
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generate
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generate
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if (debug==1) begin : debug_we
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if (debug==1) begin : debug_we
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always @ (posedge clk)
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always @ (posedge clk)
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if (we3)
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if (we3)
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$display ("Value %h written at register %h : time %t", wd3, a3, $time);
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$display ("Value %h written at register %h : time %t", wd3, a3, $time);
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end
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end
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endgenerate
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endgenerate
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reg [data_width-1:0] wd3_reg;
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vl_dpram_1r1w
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reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
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# ( .data_width(dw), .addr_width(aw))
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reg we3_reg;
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ram1 (
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reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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.d_a(wd3),
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reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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.adr_a(a3),
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.we_a(we3),
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.clk_a(clk),
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.q_b(rd1mem),
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.adr_b(a1),
|
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.clk_b(clk) );
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vl_dpram_1r1w
|
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# ( .data_width(dw), .addr_width(aw))
|
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ram2 (
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.d_a(wd3),
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.adr_a(a3),
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.we_a(we3),
|
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.clk_a(clk),
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.q_b(rd2mem),
|
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.adr_b(a2),
|
|
.clk_b(clk) );
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
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{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
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else
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else
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{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
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{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
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always @ (negedge clk)
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assign rd1 = (sel1) ? wreg : rd1mem;
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if (we3_reg)
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assign rd2 = (sel2) ? wreg : rd2mem;
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ram1[a3_reg] <= wd3;
|
|
always @ (posedge clk)
|
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a1_reg <= a1;
|
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assign rd1 = ram1[a1_reg];
|
|
always @ (negedge clk)
|
|
if (we3_reg)
|
|
ram2[a3_reg] <= wd3;
|
|
always @ (posedge clk)
|
|
a2_reg <= a2;
|
|
assign rd2 = ram2[a2_reg];
|
|
endmodule
|
endmodule
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//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
|
//// Versatile library, wishbone stuff ////
|
//// Versatile library, wishbone stuff ////
|
//// ////
|
//// ////
|
