URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 72 and 73

Rev 72	Rev 73
Line 1123...	Line 1123...
`parameter data_width = 32;`	`parameter data_width = 32;`
`parameter addr_width = 6;`	`parameter addr_width = 6;`
`parameter mem_size = 256;`	`parameter mem_size = 256;`
`input [(data_width-1):0] d;`	`input [(data_width-1):0] d;`
`input [(addr_width-1):0] adr;`	`input [(addr_width-1):0] adr;`
`input [(addr_width/4)-1:0] be;`	`input [(data_width/8)-1:0] be;`
`input we;`	`input we;`
`output reg [(data_width-1):0] q;`	`output reg [(data_width-1):0] q;`
`input clk;`	`input clk;`
`ifdef SYSTEMVERILOG	`ifdef SYSTEMVERILOG
`logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width`	`logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width`