| Line 1292... |
Line 1292... |
$readmemh(memory_file, rom);
|
$readmemh(memory_file, rom);
|
end
|
end
|
always @ (posedge clk)
|
always @ (posedge clk)
|
q <= rom[adr];
|
q <= rom[adr];
|
endmodule
|
endmodule
|
module vl_rom ( adr, q, clk);
|
/*
|
parameter data_width = 32;
|
module vl_rom ( adr, q, clk);
|
parameter addr_width = 4;
|
parameter data_width = 32;
|
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
|
parameter addr_width = 4;
|
{32'h18000000},
|
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
|
{32'hA8200000},
|
{32'h18000000},
|
{32'hA8200000},
|
{32'hA8200000},
|
{32'hA8200000},
|
{32'hA8200000},
|
{32'h44003000},
|
{32'hA8200000},
|
{32'h15000000},
|
{32'h44003000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000},
|
{32'h15000000}};
|
{32'h15000000},
|
input [addr_width-1:0] adr;
|
{32'h15000000}};
|
output reg [data_width-1:0] q;
|
input [addr_width-1:0] adr;
|
input clk;
|
output reg [data_width-1:0] q;
|
always @ (posedge clk)
|
input clk;
|
q <= data[adr];
|
always @ (posedge clk)
|
endmodule
|
q <= data[adr];
|
|
endmodule
|
|
*/
|
// Single port RAM
|
// Single port RAM
|
module vl_ram ( d, adr, we, q, clk);
|
module vl_ram ( d, adr, we, q, clk);
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
input [(data_width-1):0] d;
|
input [(data_width-1):0] d;
|
| Line 1480... |
Line 1482... |
parameter Q3 = 2'b11;
|
parameter Q3 = 2'b11;
|
parameter Q4 = 2'b10;
|
parameter Q4 = 2'b10;
|
parameter going_empty = 1'b0;
|
parameter going_empty = 1'b0;
|
parameter going_full = 1'b1;
|
parameter going_full = 1'b1;
|
input [N:0] wptr, rptr;
|
input [N:0] wptr, rptr;
|
output reg fifo_empty;
|
output fifo_empty;
|
output fifo_full;
|
output fifo_full;
|
input wclk, rclk, rst;
|
input wclk, rclk, rst;
|
wire direction;
|
wire direction;
|
reg direction_set, direction_clr;
|
reg direction_set, direction_clr;
|
wire async_empty, async_full;
|
wire async_empty, async_full;
|
wire fifo_full2;
|
wire fifo_full2;
|
reg fifo_empty2;
|
wire fifo_empty2;
|
// direction_set
|
// direction_set
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
{Q1,Q2} : direction_set <= 1'b1;
|
{Q1,Q2} : direction_set <= 1'b1;
|
{Q2,Q3} : direction_set <= 1'b1;
|
{Q2,Q3} : direction_set <= 1'b1;
|
| Line 1523... |
Line 1525... |
else if (async_full)
|
else if (async_full)
|
{fifo_full, fifo_full2} <= 2'b11;
|
{fifo_full, fifo_full2} <= 2'b11;
|
else
|
else
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
*/
|
*/
|
always @ (posedge rclk or posedge async_empty)
|
/* always @ (posedge rclk or posedge async_empty)
|
if (async_empty)
|
if (async_empty)
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
else
|
else
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
|
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
|
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
endmodule // async_comp
|
endmodule // async_comp
|
module vl_fifo_1r1w_async (
|
module vl_fifo_1r1w_async (
|
d, wr, fifo_full, wr_clk, wr_rst,
|
d, wr, fifo_full, wr_clk, wr_rst,
|
q, rd, fifo_empty, rd_clk, rd_rst
|
q, rd, fifo_empty, rd_clk, rd_rst
|
);
|
);
|
| Line 1722... |
Line 1726... |
input [3:0] wbs_sel_i;
|
input [3:0] wbs_sel_i;
|
input [1:0] wbs_bte_i;
|
input [1:0] wbs_bte_i;
|
input [2:0] wbs_cti_i;
|
input [2:0] wbs_cti_i;
|
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
|
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
|
output [31:0] wbs_dat_o;
|
output [31:0] wbs_dat_o;
|
output reg wbs_ack_o;
|
output wbs_ack_o;
|
input wbs_clk, wbs_rst;
|
input wbs_clk, wbs_rst;
|
output [31:0] wbm_dat_o;
|
output [31:0] wbm_dat_o;
|
output reg [31:2] wbm_adr_o;
|
output reg [31:2] wbm_adr_o;
|
output [3:0] wbm_sel_o;
|
output [3:0] wbm_sel_o;
|
output reg [1:0] wbm_bte_o;
|
output reg [1:0] wbm_bte_o;
|
output reg [2:0] wbm_cti_o;
|
output reg [2:0] wbm_cti_o;
|
output reg wbm_we_o, wbm_cyc_o;
|
output reg wbm_we_o;
|
|
output wbm_cyc_o;
|
output wbm_stb_o;
|
output wbm_stb_o;
|
input [31:0] wbm_dat_i;
|
input [31:0] wbm_dat_i;
|
input wbm_ack_i;
|
input wbm_ack_i;
|
input wbm_clk, wbm_rst;
|
input wbm_clk, wbm_rst;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
| Line 1754... |
Line 1759... |
reg [1:0] wbs_bte_reg;
|
reg [1:0] wbs_bte_reg;
|
reg wbs;
|
reg wbs;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
reg wbs_eoc, wbm_eoc;
|
reg wbs_eoc, wbm_eoc;
|
reg [1:0] wbm;
|
reg [1:0] wbm;
|
reg [1:16] wbs_count, wbm_count;
|
wire [1:16] wbs_count, wbm_count;
|
wire [35:0] a_d, a_q, b_d, b_q;
|
wire [35:0] a_d, a_q, b_d, b_q;
|
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
|
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
|
reg a_rd_reg;
|
reg a_rd_reg;
|
wire b_rd_adr, b_rd_data;
|
wire b_rd_adr, b_rd_data;
|
reg b_rd_data_reg;
|
wire b_rd_data_reg;
|
reg [35:0] temp;
|
wire [35:0] temp;
|
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
|
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs_eoc <= 1'b0;
|
wbs_eoc <= 1'b0;
|
else
|
else
|
