Subversion Repositories versatile_library

   output [length:1] q;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire [length:1] q_next;

   assign q_next = qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

       qi <= q_next;

   assign q = qi;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin_clear ( clear, q, rst, clk);

   parameter length = 4;

   input clear;

   output [length:1] q;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire [length:1] q_next;

   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

       qi <= q_next;

   assign q = qi;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin_ce ( cke, q, rst, clk);

   parameter length = 4;

   input cke;

   output [length:1] q;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire [length:1] q_next;

   assign q_next = qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

   assign q = qi;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);

   parameter length = 4;

   input clear;

   input cke;

   output [length:1] q;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire [length:1] q_next;

   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

   assign q = qi;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);

   parameter length = 4;

   input clear;

   input cke;

   output [length:1] q;

   output reg level1;

   output reg level2;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 15;

   parameter level1_value = 8;

   parameter level2_value = 15;

   wire rew;

   assign rew = 1'b0;

   reg  [length:1] qi;

   wire [length:1] q_next;

   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

   assign q = qi;

    always @ (posedge clk or posedge rst)

    if (rst)

        level1 <= 1'b0;

    else

    if (cke)

    if (clear)

        level1 <= 1'b0;

    else if (q_next == level1_value)

        level1 <= 1'b1;

    else if (qi == level1_value & rew)

        level1 <= 1'b0;

    always @ (posedge clk or posedge rst)

    if (rst)

        level2 <= 1'b0;

    else

    if (cke)

    if (clear)

        level2 <= 1'b0;

    else if (q_next == level2_value)

        level2 <= 1'b1;

    else if (qi == level2_value & rew)

        level2 <= 1'b0;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);

   parameter length = 4;

   input clear;

   input set;

   input cke;

   input rew;

   output [length:1] q;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire  [length:1] q_next, q_next_fw, q_next_rew;

   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};

   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};

   assign q_next = rew ? q_next_rew : q_next_fw;

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

   assign q = qi;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);

   parameter length = 4;

   input cke;

   input rew;

   output reg level1;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 1;

   parameter level1_value = 15;

   wire clear;

   assign clear = 1'b0;

   reg  [length:1] qi;

   wire  [length:1] q_next, q_next_fw, q_next_rew;

   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};

   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};

   assign q_next = rew ? q_next_rew : q_next_fw;

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

    always @ (posedge clk or posedge rst)

    if (rst)

        level1 <= 1'b0;

    else

    if (cke)

    if (clear)

        level1 <= 1'b0;

    else if (q_next == level1_value)

        level1 <= 1'b1;

    else if (qi == level1_value & rew)

        level1 <= 1'b0;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);

   parameter length = 4;

   input cke;

   input rew;

   output reg zq;

   output reg level1;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 1;

   parameter level1_value = 15;

   wire clear;

   assign clear = 1'b0;

   reg  [length:1] qi;

   wire  [length:1] q_next, q_next_fw, q_next_rew;

   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};

   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};

   assign q_next = rew ? q_next_rew : q_next_fw;

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

   always @ (posedge clk or posedge rst)

     if (rst)

       zq <= 1'b1;

     else

     if (cke)

       zq <= q_next == {length{1'b0}};

    always @ (posedge clk or posedge rst)

    if (rst)

        level1 <= 1'b0;

    else

    if (cke)

    if (clear)

        level1 <= 1'b0;

    else if (q_next == level1_value)

        level1 <= 1'b1;

    else if (qi == level1_value & rew)

        level1 <= 1'b0;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);

   parameter length = 4;

   input cke;

   input rew;

   output [length:1] q;

   output reg zq;

   output reg level1;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 1;

   parameter level1_value = 15;

   wire clear;

   assign clear = 1'b0;

   reg  [length:1] qi;

   wire  [length:1] q_next, q_next_fw, q_next_rew;

   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};

   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};

   assign q_next = rew ? q_next_rew : q_next_fw;

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

     if (cke)

       qi <= q_next;

   assign q = qi;

   always @ (posedge clk or posedge rst)

     if (rst)

       zq <= 1'b1;

     else

     if (cke)

       zq <= q_next == {length{1'b0}};

    always @ (posedge clk or posedge rst)

    if (rst)

        level1 <= 1'b0;

    else

    if (cke)

    if (clear)

        level1 <= 1'b0;

    else if (q_next == level1_value)

        level1 <= 1'b1;

    else if (qi == level1_value & rew)

        level1 <= 1'b0;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// LFSR counter

module vl_cnt_lfsr_zq ( zq, rst, clk);

   parameter length = 4;

   output reg zq;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 8;

   parameter level1_value = 15;

   reg  [length:1] qi;

   reg lfsr_fb;

   wire [length:1] q_next;

   reg [32:1] polynom;

   integer i;

   always @ (qi)

   begin

        case (length)

         2: polynom = 32'b11;                               // 0x3

         3: polynom = 32'b110;                              // 0x6

         4: polynom = 32'b1100;                             // 0xC

         5: polynom = 32'b10100;                            // 0x14

         6: polynom = 32'b110000;                           // 0x30

         7: polynom = 32'b1100000;                          // 0x60

         8: polynom = 32'b10111000;                         // 0xb8

         9: polynom = 32'b100010000;                        // 0x110

        10: polynom = 32'b1001000000;                       // 0x240

        11: polynom = 32'b10100000000;                      // 0x500

        12: polynom = 32'b100000101001;                     // 0x829

        13: polynom = 32'b1000000001100;                    // 0x100C

        14: polynom = 32'b10000000010101;                   // 0x2015

        15: polynom = 32'b110000000000000;                  // 0x6000

        16: polynom = 32'b1101000000001000;                 // 0xD008

        17: polynom = 32'b10010000000000000;                // 0x12000

        18: polynom = 32'b100000010000000000;               // 0x20400

        19: polynom = 32'b1000000000000100011;              // 0x40023

        20: polynom = 32'b10010000000000000000;             // 0x90000

        21: polynom = 32'b101000000000000000000;            // 0x140000

        22: polynom = 32'b1100000000000000000000;           // 0x300000

        23: polynom = 32'b10000100000000000000000;          // 0x420000

        24: polynom = 32'b111000010000000000000000;         // 0xE10000

        25: polynom = 32'b1001000000000000000000000;        // 0x1200000

        26: polynom = 32'b10000000000000000000100011;       // 0x2000023

        27: polynom = 32'b100000000000000000000010011;      // 0x4000013

        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000

        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000

        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029

        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000

        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003

        default: polynom = 32'b0;

        endcase

        lfsr_fb = qi[length];

        for (i=length-1; i>=1; i=i-1) begin

            if (polynom[i])

                lfsr_fb = lfsr_fb  ~^ qi[i];

        end

    end

   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

       qi <= q_next;

   always @ (posedge clk or posedge rst)

     if (rst)

       zq <= 1'b1;

     else

       zq <= q_next == {length{1'b0}};

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////