| Line 37... |
Line 37... |
//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// Global buffer
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// usage:
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// use to enable global buffers for high fan out signals such as clock and reset
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//altera
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//altera
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module vl_gbuf ( i, o);
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module vl_gbuf ( i, o);
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input i;
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input i;
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output o;
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output o;
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assign o = i;
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assign o = i;
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| Line 1201... |
Line 1198... |
$readmemh(memory_file, rom);
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$readmemh(memory_file, rom);
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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q <= rom[adr];
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q <= rom[adr];
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endmodule
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endmodule
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/*
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module vl_rom ( adr, q, clk);
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parameter data_width = 32;
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parameter addr_width = 4;
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parameter [0:1>>addr_width-1] data [data_width-1:0] = {
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{32'h18000000},
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{32'hA8200000},
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{32'hA8200000},
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{32'hA8200000},
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{32'h44003000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000}};
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input [addr_width-1:0] adr;
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output reg [data_width-1:0] q;
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input clk;
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always @ (posedge clk)
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q <= data[adr];
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endmodule
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*/
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// Single port RAM
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// Single port RAM
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module vl_ram ( d, adr, we, q, clk);
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module vl_ram ( d, adr, we, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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| Line 1284... |
Line 1253... |
end
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end
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endgenerate
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endgenerate
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always @ (posedge clk)
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always @ (posedge clk)
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q <= ram[adr];
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q <= ram[adr];
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endmodule
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endmodule
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// Dual port RAM
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// ACTEL FPGA should not use logic to handle rw collision
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module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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| Line 1676... |
Line 1643... |
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
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cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
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vl_fifo_cmp_async
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vl_fifo_cmp_async
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# (.addr_width(addr_width))
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# (.addr_width(addr_width))
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cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
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cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
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endmodule
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endmodule
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module vl_reg_file (
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a1, a2, a3, wd3, we3, rd1, rd2, clk
|
|
);
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parameter data_width = 32;
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parameter addr_width = 5;
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input [addr_width-1:0] a1, a2, a3;
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input [data_width-1:0] wd3;
|
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input we3;
|
|
output [data_width-1:0] rd1, rd2;
|
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input clk;
|
|
vl_dpram_1r1w
|
|
# ( .data_width(data_width), .addr_width(addr_width))
|
|
ram1 (
|
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.d_a(wd3),
|
|
.adr_a(a3),
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.we_a(we3),
|
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.clk_a(clk),
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.q_b(rd1),
|
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.adr_b(a1),
|
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.clk_b(clk) );
|
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vl_dpram_1r1w
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# ( .data_width(data_width), .addr_width(addr_width))
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ram2 (
|
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.d_a(wd3),
|
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.adr_a(a3),
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.we_a(we3),
|
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.clk_a(clk),
|
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.q_b(rd2),
|
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.adr_b(a2),
|
|
.clk_b(clk) );
|
|
endmodule
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//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
|
//// Versatile library, wishbone stuff ////
|
//// Versatile library, wishbone stuff ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
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| Line 2049... |
Line 2047... |
assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
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assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
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assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
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assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
|
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
endmodule
|
endmodule
|
// WB ROM
|
// WB ROM
|
|
module vl_wb_b4_rom (
|
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
|
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
|
|
parameter dat_width = 32;
|
|
parameter dat_default = 32'h15000000;
|
|
parameter adr_width = 32;
|
|
/*
|
|
`ifndef ROM
|
|
`define ROM "rom.v"
|
|
`endif
|
|
*/
|
|
input [adr_width-1:2] wb_adr_i;
|
|
input wb_stb_i;
|
|
input wb_cyc_i;
|
|
output [dat_width-1:0] wb_dat_o;
|
|
reg [dat_width-1:0] wb_dat_o;
|
|
output wb_ack_o;
|
|
reg wb_ack_o;
|
|
output stall_o;
|
|
input wb_clk;
|
|
input wb_rst;
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
|
if (wb_rst)
|
|
wb_dat_o <= {dat_width{1'b0}};
|
|
else
|
|
case (wb_adr_i[adr_width-1:2])
|
|
`ifdef ROM
|
|
`include `ROM
|
|
`endif
|
|
default:
|
|
wb_dat_o <= dat_default;
|
|
endcase // case (wb_adr_i)
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
|
if (wb_rst)
|
|
wb_ack_o <= 1'b0;
|
|
else
|
|
wb_ack_o <= wb_stb_i & wb_cyc_i;
|
|
assign stall_o = 1'b0;
|
|
endmodule
|
|
// WB ROM
|
module vl_wb_boot_rom (
|
module vl_wb_boot_rom (
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
parameter adr_hi = 31;
|
parameter adr_hi = 31;
|
parameter adr_lo = 28;
|
parameter adr_lo = 28;
|
| Line 2325... |
Line 2363... |
assign result = (opcode==opcode_and) ? a & b :
|
assign result = (opcode==opcode_and) ? a & b :
|
(opcode==opcode_or) ? a | b :
|
(opcode==opcode_or) ? a | b :
|
(opcode==opcode_xor) ? a ^ b :
|
(opcode==opcode_xor) ? a ^ b :
|
b;
|
b;
|
endmodule
|
endmodule
|
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
|
|
parameter width = 32;
|
|
parameter opcode_add = 1'b0;
|
|
parameter opcode_sub = 1'b1;
|
|
input [width-1:0] a,b;
|
|
input c_in, add_sub, sign;
|
|
output [width-1:0] result;
|
|
output c_out, z, ovfl;
|
|
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
|
|
assign z = (result=={width{1'b0}});
|
|
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
|
|
(~a[width-1] & ~b[width-1] & result[width-1]);
|
|
endmodule
|
|
|
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No newline at end of file
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No newline at end of file
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