URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 54 and 55

Rev 54	Rev 55
Line 2079...	Line 2079...
`wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};`	`wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};`
`end`	`end`
`end`	`end`
`endgenerate`	`endgenerate`
`always @ (posedge wb_clk or posedge wb_rst)`	`always @ (posedge wb_clk or posedge wb_rst)`
`if (rst)`	`if (wb_rst)`
`wb_ack_o <= 1'b0;`	`wb_ack_o <= 1'b0;`
`else`	`else`
`wb_ack_o <= wb_stb_i & wb_cyc_i;`	`wb_ack_o <= wb_stb_i & wb_cyc_i;`
`assign wb_stall_o = 1'b0;`	`assign wb_stall_o = 1'b0;`
`endmodule`	`endmodule`