URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 70 and 71

Rev 70	Rev 71
Line 2174...	Line 2174...
`input [bw-1:0] wbs_bte_i;`	`input [bw-1:0] wbs_bte_i;`
`input [sw-1:0] wbs_sel_i;`	`input [sw-1:0] wbs_sel_i;`
`input wbs_we_i, wbs_stb_i, wbs_cyc_i;`	`input wbs_we_i, wbs_stb_i, wbs_cyc_i;`
`output [dw-1:0] wbs_dat_o;`	`output [dw-1:0] wbs_dat_o;`
`output wbs_ack_o;`	`output wbs_ack_o;`
`input wbs_clk, wbs_rst;`	`input wb_clk, wb_rst;`
`wire [sw-1:0] cke;`	`wire [sw-1:0] cke;`
`reg wbs_ack_o;`	`reg wbs_ack_o;`
`vl_ram_be # (`	`vl_ram_be # (`
`.data_width(dat_size),`	`.data_width(dat_size),`
`.addr_width(adr_size),`	`.addr_width(adr_size),`