URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 85 and 86

Rev 85	Rev 86
Line 1372...	Line 1372...
`// use a multi-dimensional packed array`	`// use a multi-dimensional packed array`
`//to model individual bytes within the word`	`//to model individual bytes within the word`
`always_ff@(posedge clk)`	`always_ff@(posedge clk)`
`begin`	`begin`
`if(we) begin // note: we should have a for statement to support any bus width`	`if(we) begin // note: we should have a for statement to support any bus width`
`if(be[3]) ram[adr[3] <= d[31:24];`	`if(be[3]) ram[adr][3] <= d[31:24];`
`if(be[2]) ram[adr[2] <= d[23:16];`	`if(be[2]) ram[adr][2] <= d[23:16];`
`if(be[1]) ram[adr[1] <= d[15:8];`	`if(be[1]) ram[adr][1] <= d[15:8];`
`if(be[0]) ram[adr[0] <= d[7:0];`	`if(be[0]) ram[adr][0] <= d[7:0];`
`end`	`end`
`q <= ram[adr];`	`q <= ram[adr];`
`end`	`end`
`else	`else
`assign cke = {data_width/8{we}} & be;`	`assign cke = {data_width/8{we}} & be;`
Line 2688...	Line 2688...
`.memory_file(memory_file))`	`.memory_file(memory_file))`
`ram0(`	`ram0(`
`.d(wbs_dat_i),`	`.d(wbs_dat_i),`
`.adr(adr),`	`.adr(adr),`
`.be(wbs_sel_i),`	`.be(wbs_sel_i),`
`.we(wbs_we_i & wb_ack_o),`	`.we(wbs_we_i & wbs_ack_o),`
`.q(wbs_dat_o),`	`.q(wbs_dat_o),`
`.clk(wb_clk)`	`.clk(wb_clk)`
`);`	`);`
`vl_wb_adr_inc # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (`	`vl_wb_adr_inc # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (`
`.cyc_i(wbs_cyc_i),`	`.cyc_i(wbs_cyc_i),`