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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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| Rev 130 |
Rev 131 |
| Line 1378... |
Line 1378... |
assign we = wbs_cyc_i & wbs_we_i & wbs_ack_o;
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assign we = wbs_cyc_i & wbs_we_i & wbs_ack_o;
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end else if (wbs_mode=="B4") begin : inst_b4
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end else if (wbs_mode=="B4") begin : inst_b4
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end
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end
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endgenerate
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endgenerate
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localparam cache_mem_b_aw =
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(dw_s==dw_m) ? aw_slot+aw_offset :
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(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
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(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
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(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
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(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
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(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
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(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
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(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
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(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
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`define MODULE dpram_be_2r2w
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`define MODULE dpram_be_2r2w
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`BASE`MODULE
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`BASE`MODULE
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# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
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# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
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cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
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cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
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