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Line 1315... |
wire done, mem_alert, mem_done;
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wire done, mem_alert, mem_done;
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// wbm side
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// wbm side
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reg [aw_m-1:0] wbm_radr;
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reg [aw_m-1:0] wbm_radr;
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reg [aw_m-1:0] wbm_wadr;
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reg [aw_m-1:0] wbm_wadr;
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wire [aw_slot-1:0] wbm_adr;
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//wire [aw_slot-1:0] wbm_adr;
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wire [aw_m-1:0] wbm_adr;
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wire wbm_radr_cke, wbm_wadr_cke;
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wire wbm_radr_cke, wbm_wadr_cke;
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reg [2:0] phase;
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reg [2:0] phase;
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// phase = {we,stb,cyc}
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// phase = {we,stb,cyc}
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localparam wbm_wait = 3'b000;
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localparam wbm_wait = 3'b000;
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Line 1521... |
endgenerate
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endgenerate
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assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
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assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
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assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
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assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
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assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
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assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
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assign wbm_sel_o = {dw_m/8{1'b1}};
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assign wbm_sel_o = {dw_m/8{1'b1}};
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assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
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assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
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assign wbm_bte_o = bte;
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assign wbm_bte_o = bte;
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assign {wbm_we_o, wbm_stb_o, wbm_cyc_o} = phase;
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assign {wbm_we_o, wbm_stb_o, wbm_cyc_o} = phase;
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