| Line 53... |
Line 53... |
input [3:0] wbs_sel_i;
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input [3:0] wbs_sel_i;
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input [1:0] wbs_bte_i;
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input [1:0] wbs_bte_i;
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input [2:0] wbs_cti_i;
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input [2:0] wbs_cti_i;
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input wbs_we_i, wbs_cyc_i, wbs_stb_i;
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input wbs_we_i, wbs_cyc_i, wbs_stb_i;
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output [31:0] wbs_dat_o;
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output [31:0] wbs_dat_o;
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output reg wbs_ack_o;
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output wbs_ack_o;
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input wbs_clk, wbs_rst;
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input wbs_clk, wbs_rst;
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output [31:0] wbm_dat_o;
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output [31:0] wbm_dat_o;
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output reg [31:2] wbm_adr_o;
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output reg [31:2] wbm_adr_o;
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output [3:0] wbm_sel_o;
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output [3:0] wbm_sel_o;
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output reg [1:0] wbm_bte_o;
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output reg [1:0] wbm_bte_o;
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output reg [2:0] wbm_cti_o;
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output reg [2:0] wbm_cti_o;
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output reg wbm_we_o, wbm_cyc_o;
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output reg wbm_we_o;
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output wbm_cyc_o;
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output wbm_stb_o;
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output wbm_stb_o;
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input [31:0] wbm_dat_i;
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input [31:0] wbm_dat_i;
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input wbm_ack_i;
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input wbm_ack_i;
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input wbm_clk, wbm_rst;
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input wbm_clk, wbm_rst;
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| Line 92... |
Line 93... |
reg wbs;
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reg wbs;
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wire wbs_eoc_alert, wbm_eoc_alert;
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wire wbs_eoc_alert, wbm_eoc_alert;
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reg wbs_eoc, wbm_eoc;
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reg wbs_eoc, wbm_eoc;
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reg [1:0] wbm;
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reg [1:0] wbm;
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reg [1:16] wbs_count, wbm_count;
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wire [1:16] wbs_count, wbm_count;
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wire [35:0] a_d, a_q, b_d, b_q;
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wire [35:0] a_d, a_q, b_d, b_q;
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wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
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wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
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reg a_rd_reg;
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reg a_rd_reg;
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wire b_rd_adr, b_rd_data;
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wire b_rd_adr, b_rd_data;
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reg b_rd_data_reg;
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wire b_rd_data_reg;
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reg [35:0] temp;
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wire [35:0] temp;
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`define WE 5
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`define WE 5
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`define BTE 4:3
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`define BTE 4:3
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`define CTI 2:0
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`define CTI 2:0
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