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Line 40... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// async wb3 - wb3 bridge
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// async wb3 - wb3 bridge
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module wb3wb3_bridge (
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module vl_wb3wb3_bridge (
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// wishbone slave side
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// wishbone slave side
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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// wishbone master side
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// wishbone master side
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
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| Line 116... |
Line 116... |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
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if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
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wbs_eoc <= wbs_bte_i==linear;
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wbs_eoc <= wbs_bte_i==linear;
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else if (wbs_eoc_alert & (a_rd | a_wr))
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else if (wbs_eoc_alert & (a_rd | a_wr))
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wbs_eoc <= 1'b1;
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wbs_eoc <= 1'b1;
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cnt_shreg_ce_clear # ( .length(16))
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vl_cnt_shreg_ce_clear # ( .length(16))
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cnt0 (
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cnt0 (
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.cke(wbs_ack_o),
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.cke(wbs_ack_o),
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.clear(wbs_eoc),
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.clear(wbs_eoc),
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.q(wbs_count),
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.q(wbs_count),
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.rst(wbs_rst),
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.rst(wbs_rst),
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| Line 183... |
Line 183... |
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
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assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
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(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
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(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
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1'b0;
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1'b0;
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assign b_rd = b_rd_adr | b_rd_data;
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assign b_rd = b_rd_adr | b_rd_data;
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dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
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vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
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dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
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vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
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assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
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assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
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cnt_shreg_ce_clear # ( .length(16))
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vl_cnt_shreg_ce_clear # ( .length(16))
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cnt1 (
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cnt1 (
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.cke(wbm_ack_i),
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.cke(wbm_ack_i),
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.clear(wbm_eoc),
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.clear(wbm_eoc),
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.q(wbm_count),
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.q(wbm_count),
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.rst(wbm_rst),
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.rst(wbm_rst),
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| Line 238... |
Line 238... |
);
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);
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endmodule
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endmodule
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// WB ROM
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// WB ROM
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module wb_boot_rom (
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module vl_wb_boot_rom (
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wb_adr_i, wb_stb_i, wb_cyc_i,
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wb_adr_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
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parameter adr_hi = 31;
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parameter adr_lo = 28;
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parameter adr_sel = 4'hf;
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parameter addr_width = 5;
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//E2_ifndef BOOT_ROM
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//E2_ifndef BOOT_ROM
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//E2_define BOOT_ROM "boot_rom.v"
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//E2_define BOOT_ROM "boot_rom.v"
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//E2_endif
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//E2_endif
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parameter addr_width = 5;
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input [(addr_width+2)-1:2] wb_adr_i;
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input [adr_hi:2] wb_adr_i;
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input wb_stb_i;
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input wb_stb_i;
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input wb_cyc_i;
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input wb_cyc_i;
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output reg [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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output reg wb_ack_o;
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output wb_ack_o;
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output hit_o;
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input wb_clk;
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input wb_clk;
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input wb_rst;
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input wb_rst;
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wire hit;
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reg [31:0] wb_dat;
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reg wb_ack;
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assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
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always @ (posedge wb_clk or posedge wb_rst)
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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if (wb_rst)
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wb_dat_o <= 32'h15000000;
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wb_dat <= 32'h15000000;
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else
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else
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case (wb_adr_i)
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case (wb_adr_i[addr_width-1:2])
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//E2_include `BOOT_ROM
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//E2_include `BOOT_ROM
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/*
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/*
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// Zero r0 and jump to 0x00000100
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// Zero r0 and jump to 0x00000100
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0 : wb_dat_o <= 32'h18000000;
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0 : wb_dat <= 32'h18000000;
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1 : wb_dat_o <= 32'hA8200000;
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1 : wb_dat <= 32'hA8200000;
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2 : wb_dat_o <= 32'hA8C00100;
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2 : wb_dat <= 32'hA8C00100;
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3 : wb_dat_o <= 32'h44003000;
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3 : wb_dat <= 32'h44003000;
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4 : wb_dat_o <= 32'h15000000;
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4 : wb_dat <= 32'h15000000;
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*/
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*/
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default:
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default:
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wb_dat_o <= 32'h00000000;
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wb_dat <= 32'h00000000;
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endcase // case (wb_adr_i)
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endcase // case (wb_adr_i)
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always @ (posedge wb_clk or posedge wb_rst)
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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if (wb_rst)
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wb_ack_o <= 1'b0;
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wb_ack <= 1'b0;
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else
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else
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wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
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wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
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assign hit_o = hit;
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assign wb_dat_o = wb_dat & {32{wb_ack}};
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assign wb_ack_o = wb_ack;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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