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assign wb_dat_o = wb_dat & {32{wb_ack}};
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assign wb_dat_o = wb_dat & {32{wb_ack}};
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assign wb_ack_o = wb_ack;
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assign wb_ack_o = wb_ack;
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endmodule
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endmodule
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module vl_wb_dpram (
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// wishbone slave side a
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wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
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wbsa_clk, wbsa_rst,
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// wishbone slave side a
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wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
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wbsb_clk, wbsb_rst);
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter dat_o_mask_a = 1;
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parameter dat_o_mask_b = 1;
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input [31:0] wbsa_dat_i;
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input [addr_width-1:2] wbsa_adr_i;
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input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
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output [31:0] wbsa_dat_o;
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output wbsa_ack_o;
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input wbsa_clk, wbsa_rst;
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input [31:0] wbsb_dat_i;
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input [addr_width-1:2] wbsb_adr_i;
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input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
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output [31:0] wbsb_dat_o;
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output wbsb_ack_o;
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input wbsb_clk, wbsb_rst;
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wire wbsa_dat_tmp, wbsb_dat_tmp;
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vl_dpram_2r2w # (
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.data_width(data_width), addr_width(addr_width) )
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dpram0(
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.d_a(wbsa_dat_i),
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.q_a(wbsa_dat_tmp),
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.adr_a(wbsa_adr_i),
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.we_a(wbsa_we_i),
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.clk_a(wbsa_clk),
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.d_b(wbsb_dat_i),
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.q_b(wbsb_dat_tmp),
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.adr_b(wbsb_adr_i),
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.we_b(wbsb_we_i),
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.clk_b(wbsb_clk) );
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if (dat_o_mask_a==1) generate
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assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
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endgenerate
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if (dat_o_mask_a==0) generate
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assign wbsa_dat_o = wbsa_dat_tmp;
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endgenerate
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if (dat_o_mask_b==1) generate
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assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
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endgenerate
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if (dat_o_mask_b==0) generate
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assign wbsb_dat_o = wbsb_dat_tmp;
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endgenerate
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vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
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vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
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endmodule
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