| Line 86... |
Line 86... |
parameter wbs_data = 1'b1;
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parameter wbs_data = 1'b1;
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parameter wbm_adr0 = 2'b00;
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parameter wbm_adr0 = 2'b00;
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parameter wbm_adr1 = 2'b01;
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parameter wbm_adr1 = 2'b01;
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parameter wbm_data = 2'b10;
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parameter wbm_data = 2'b10;
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parameter wbm_data_wait = 2'b11;
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reg [1:0] wbs_bte_reg;
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reg [1:0] wbs_bte_reg;
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reg wbs;
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reg wbs;
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wire wbs_eoc_alert, wbm_eoc_alert;
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wire wbs_eoc_alert, wbm_eoc_alert;
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reg wbs_eoc, wbm_eoc;
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reg wbs_eoc, wbm_eoc;
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| Line 169... |
Line 170... |
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always @ (posedge wbm_clk or posedge wbm_rst)
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always @ (posedge wbm_clk or posedge wbm_rst)
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if (wbm_rst)
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if (wbm_rst)
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wbm <= wbm_adr0;
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wbm <= wbm_adr0;
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else
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else
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if ((wbm==wbm_adr0 & !b_fifo_empty) |
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/*
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(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
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if ((wbm==wbm_adr0 & !b_fifo_empty) |
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(wbm==wbm_adr1 & !wbm_we_o) |
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(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
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(wbm==wbm_data & wbm_ack_i & wbm_eoc))
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(wbm==wbm_adr1 & !wbm_we_o) |
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wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
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(wbm==wbm_data & wbm_ack_i & wbm_eoc))
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wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
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*/
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case (wbm)
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wbm_adr0:
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if (!b_fifo_empty)
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wbm <= wbm_adr1;
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wbm_adr1:
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if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
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wbm <= wbm_data;
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wbm_data:
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if (wbm_ack_i & wbm_eoc)
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wbm <= wbm_adr0;
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else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
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wbm <= wbm_data_wait;
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wbm_data_wait:
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if (!b_fifo_empty)
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wbm <= wbm_data;
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endcase
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assign b_d = {wbm_dat_i,4'b1111};
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assign b_d = {wbm_dat_i,4'b1111};
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assign b_wr = !wbm_we_o & wbm_ack_i;
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assign b_wr = !wbm_we_o & wbm_ack_i;
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assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
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assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
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assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
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assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
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(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
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(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
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(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
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1'b0;
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1'b0;
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assign b_rd = b_rd_adr | b_rd_data;
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assign b_rd = b_rd_adr | b_rd_data;
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vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
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vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
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vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
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vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
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| Line 196... |
Line 216... |
.clear(wbm_eoc),
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.clear(wbm_eoc),
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.q(wbm_count),
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.q(wbm_count),
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.rst(wbm_rst),
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.rst(wbm_rst),
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.clk(wbm_clk));
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.clk(wbm_clk));
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assign wbm_cyc_o = wbm==wbm_data;
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assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
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assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
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assign wbm_stb_o = (wbm==wbm_data);
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(wbm==wbm_data) ? 1'b1 :
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1'b0;
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always @ (posedge wbm_clk or posedge wbm_rst)
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always @ (posedge wbm_clk or posedge wbm_rst)
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if (wbm_rst)
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if (wbm_rst)
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{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
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{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
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else begin
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else begin
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| Line 246... |
Line 264... |
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parameter adr_hi = 31;
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parameter adr_hi = 31;
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parameter adr_lo = 28;
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parameter adr_lo = 28;
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parameter adr_sel = 4'hf;
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parameter adr_sel = 4'hf;
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parameter addr_width = 5;
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parameter addr_width = 5;
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/*
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//E2_ifndef BOOT_ROM
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//E2_ifndef BOOT_ROM
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//E2_define BOOT_ROM "boot_rom.v"
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//E2_define BOOT_ROM "boot_rom.v"
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//E2_endif
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//E2_endif
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*/
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input [adr_hi:2] wb_adr_i;
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input [adr_hi:2] wb_adr_i;
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input wb_stb_i;
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input wb_stb_i;
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input wb_cyc_i;
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input wb_cyc_i;
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output [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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output wb_ack_o;
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output wb_ack_o;
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| Line 271... |
Line 289... |
always @ (posedge wb_clk or posedge wb_rst)
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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if (wb_rst)
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wb_dat <= 32'h15000000;
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wb_dat <= 32'h15000000;
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else
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else
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case (wb_adr_i[addr_width-1:2])
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case (wb_adr_i[addr_width-1:2])
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//E2_ifdef BOOT_ROM
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//E2_include `BOOT_ROM
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//E2_include `BOOT_ROM
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//E2_endif
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/*
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/*
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// Zero r0 and jump to 0x00000100
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// Zero r0 and jump to 0x00000100
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0 : wb_dat <= 32'h18000000;
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0 : wb_dat <= 32'h18000000;
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1 : wb_dat <= 32'hA8200000;
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1 : wb_dat <= 32'hA8200000;
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2 : wb_dat <= 32'hA8C00100;
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2 : wb_dat <= 32'hA8C00100;
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| Line 329... |
Line 349... |
input wbsb_clk, wbsb_rst;
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input wbsb_clk, wbsb_rst;
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wire wbsa_dat_tmp, wbsb_dat_tmp;
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wire wbsa_dat_tmp, wbsb_dat_tmp;
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vl_dpram_2r2w # (
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vl_dpram_2r2w # (
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.data_width(data_width), addr_width(addr_width) )
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.data_width(data_width), .addr_width(addr_width) )
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dpram0(
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dpram0(
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.d_a(wbsa_dat_i),
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.d_a(wbsa_dat_i),
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.q_a(wbsa_dat_tmp),
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.q_a(wbsa_dat_tmp),
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.adr_a(wbsa_adr_i),
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.adr_a(wbsa_adr_i),
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.we_a(wbsa_we_i),
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.we_a(wbsa_we_i),
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| Line 342... |
Line 362... |
.q_b(wbsb_dat_tmp),
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.q_b(wbsb_dat_tmp),
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.adr_b(wbsb_adr_i),
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.adr_b(wbsb_adr_i),
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.we_b(wbsb_we_i),
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.we_b(wbsb_we_i),
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.clk_b(wbsb_clk) );
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.clk_b(wbsb_clk) );
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if (dat_o_mask_a==1) generate
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generate if (dat_o_mask_a==1)
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assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
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assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
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endgenerate
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endgenerate
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if (dat_o_mask_a==0) generate
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generate if (dat_o_mask_a==0)
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assign wbsa_dat_o = wbsa_dat_tmp;
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assign wbsa_dat_o = wbsa_dat_tmp;
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endgenerate
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endgenerate
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if (dat_o_mask_b==1) generate
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generate if (dat_o_mask_b==1)
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assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
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assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
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endgenerate
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endgenerate
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if (dat_o_mask_b==0) generate
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generate if (dat_o_mask_b==0)
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assign wbsb_dat_o = wbsb_dat_tmp;
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assign wbsb_dat_o = wbsb_dat_tmp;
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endgenerate
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endgenerate
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vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
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vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
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vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
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vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
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