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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`ifdef WB3WB3_BRIDGE
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// async wb3 - wb3 bridge
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// async wb3 - wb3 bridge
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module vl_wb3wb3_bridge (
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`define MODULE wb3wb3_bridge
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module `BASE`MODULE (
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`undef MODULE
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// wishbone slave side
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// wishbone slave side
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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// wishbone master side
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// wishbone master side
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
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Line 117... |
Line 120... |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
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if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
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wbs_eoc <= wbs_bte_i==linear;
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wbs_eoc <= wbs_bte_i==linear;
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else if (wbs_eoc_alert & (a_rd | a_wr))
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else if (wbs_eoc_alert & (a_rd | a_wr))
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wbs_eoc <= 1'b1;
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wbs_eoc <= 1'b1;
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vl_cnt_shreg_ce_clear # ( .length(16))
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`define MODULE cnt_shreg_ce_clear
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`BASE`MODULE # ( .length(16))
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`undef MODULE
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cnt0 (
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cnt0 (
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.cke(wbs_ack_o),
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.cke(wbs_ack_o),
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.clear(wbs_eoc),
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.clear(wbs_eoc),
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.q(wbs_count),
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.q(wbs_count),
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.rst(wbs_rst),
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.rst(wbs_rst),
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Line 203... |
Line 208... |
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
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(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
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(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
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(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
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1'b0;
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1'b0;
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assign b_rd = b_rd_adr | b_rd_data;
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assign b_rd = b_rd_adr | b_rd_data;
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vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
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`define MODULE dff
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vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
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`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
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`undef MODULE
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`define MODULE dff_ce
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`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
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`undef MODULE
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assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
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assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
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`define MODULE cnt_shreg_ce_clear
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vl_cnt_shreg_ce_clear # ( .length(16))
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vl_cnt_shreg_ce_clear # ( .length(16))
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`undef MODULE
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cnt1 (
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cnt1 (
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.cke(wbm_ack_i),
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.cke(wbm_ack_i),
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.clear(wbm_eoc),
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.clear(wbm_eoc),
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.q(wbm_count),
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.q(wbm_count),
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.rst(wbm_rst),
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.rst(wbm_rst),
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Line 230... |
Line 241... |
else if (wbm_eoc_alert & wbm_ack_i)
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else if (wbm_eoc_alert & wbm_ack_i)
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wbm_cti_o <= endofburst;
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wbm_cti_o <= endofburst;
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end
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end
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//async_fifo_dw_simplex_top
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//async_fifo_dw_simplex_top
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vl_fifo_2r2w_async_simplex
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`define MODULE fifo_2r2w_async_simplex
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`BASE`MODULE
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`undef MODULE
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# ( .data_width(36), .addr_width(addr_width))
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# ( .data_width(36), .addr_width(addr_width))
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fifo (
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fifo (
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// a side
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// a side
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.a_d(a_d),
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.a_d(a_d),
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.a_wr(a_wr),
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.a_wr(a_wr),
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Line 254... |
Line 267... |
.b_clk(wbm_clk),
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.b_clk(wbm_clk),
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.b_rst(wbm_rst)
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.b_rst(wbm_rst)
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);
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);
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endmodule
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endmodule
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`undef WE
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`undef BTE
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`undef CTI
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`endif
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`ifdef WB3_ARBITER_TYPE1
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`define MODULE wb3_arbiter_type1
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module vl_wb3_arbiter_type1 (
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module vl_wb3_arbiter_type1 (
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`undef MODULE
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
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wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
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wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
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wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
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wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
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wb_clk, wb_rst
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wb_clk, wb_rst
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Line 342... |
Line 362... |
end
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end
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endgenerate
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endgenerate
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assign sel = select | state;
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assign sel = select | state;
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vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
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`define MODULE mux_andor
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vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
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`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
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vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
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`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
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vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
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`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
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vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
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`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
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vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
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`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
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vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
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`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
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`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
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`undef MODULE
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assign wbs_cyc_i = |sel;
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assign wbs_cyc_i = |sel;
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assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
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assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
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assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
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assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
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assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
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assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
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assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
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assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
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endmodule
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endmodule
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`endif
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`ifdef WB_BOOT_ROM
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// WB ROM
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// WB ROM
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module vl_wb_boot_rom (
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`define MODULE wb_boot_rom
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module `BASE`MODULE (
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`undef MODULE
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wb_adr_i, wb_stb_i, wb_cyc_i,
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wb_adr_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
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wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
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parameter adr_hi = 31;
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parameter adr_hi = 31;
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parameter adr_lo = 28;
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parameter adr_lo = 28;
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Line 420... |
Line 446... |
assign hit_o = hit;
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assign hit_o = hit;
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assign wb_dat_o = wb_dat & {32{wb_ack}};
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assign wb_dat_o = wb_dat & {32{wb_ack}};
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assign wb_ack_o = wb_ack;
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assign wb_ack_o = wb_ack;
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endmodule
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endmodule
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`endif
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module vl_wb_dpram (
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`ifdef WB_DPRAM
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`define MODULE wb_dpram
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module `BASE`MODULE (
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`undef MODULE
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// wishbone slave side a
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// wishbone slave side a
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wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
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wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
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wbsa_clk, wbsa_rst,
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wbsa_clk, wbsa_rst,
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// wishbone slave side a
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// wishbone slave side a
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wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
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wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
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Line 451... |
Line 481... |
output wbsb_ack_o;
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output wbsb_ack_o;
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input wbsb_clk, wbsb_rst;
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input wbsb_clk, wbsb_rst;
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wire wbsa_dat_tmp, wbsb_dat_tmp;
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wire wbsa_dat_tmp, wbsb_dat_tmp;
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vl_dpram_2r2w # (
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`define MODULE dpram_2r2w
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`BASE`MODULE # (
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`undef MODULE
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.data_width(data_width), .addr_width(addr_width) )
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.data_width(data_width), .addr_width(addr_width) )
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dpram0(
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dpram0(
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.d_a(wbsa_dat_i),
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.d_a(wbsa_dat_i),
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.q_a(wbsa_dat_tmp),
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.q_a(wbsa_dat_tmp),
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.adr_a(wbsa_adr_i),
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.adr_a(wbsa_adr_i),
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Line 479... |
Line 511... |
endgenerate
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endgenerate
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generate if (dat_o_mask_b==0)
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generate if (dat_o_mask_b==0)
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assign wbsb_dat_o = wbsb_dat_tmp;
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assign wbsb_dat_o = wbsb_dat_tmp;
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endgenerate
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endgenerate
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vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
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`define MODULE spr
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vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
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`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
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`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
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`undef MODULE
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endmodule
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endmodule
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`endif
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No newline at end of file
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No newline at end of file
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