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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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| Rev 55 |
Rev 56 |
| Line 487... |
Line 487... |
output wb_stall_o;
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output wb_stall_o;
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output wb_ack_o;
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output wb_ack_o;
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reg wb_ack_o;
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reg wb_ack_o;
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input wb_clk, wb_rst;
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input wb_clk, wb_rst;
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wire [dat_width/8-1:0] cke;
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generate
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generate
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if (dat_width==32) begin
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if (dat_width==32) begin
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reg [7:0] ram3 [1<<(adr_width-2)-1:0];
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reg [7:0] ram3 [1<<(adr_width-2)-1:0];
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reg [7:0] ram2 [1<<(adr_width-2)-1:0];
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reg [7:0] ram2 [1<<(adr_width-2)-1:0];
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reg [7:0] ram1 [1<<(adr_width-2)-1:0];
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reg [7:0] ram1 [1<<(adr_width-2)-1:0];
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reg [7:0] ram0 [1<<(adr_width-2)-1:0];
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reg [7:0] ram0 [1<<(adr_width-2)-1:0];
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assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
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always @ (posedge wb_clk)
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always @ (posedge wb_clk)
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begin
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begin
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if (wb_sel_i[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
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if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
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if (wb_sel_i[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
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if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
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if (wb_sel_i[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
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if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
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if (wb_sel_i[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
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if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
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wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
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wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
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end
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end
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end
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end
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endgenerate
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endgenerate
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