URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 79 |
Rev 80 |
| Line 326... |
Line 326... |
input [31:0] readdata;
|
input [31:0] readdata;
|
output [31:0] writedata;
|
output [31:0] writedata;
|
output [31:2] address;
|
output [31:2] address;
|
output [3:0] be;
|
output [3:0] be;
|
output write;
|
output write;
|
output read;
|
output reg read;
|
output beginbursttransfer;
|
output beginbursttransfer;
|
output [3:0] burstcount;
|
output [3:0] burstcount;
|
input readdatavalid;
|
input readdatavalid;
|
input waitrequest;
|
input waitrequest;
|
input clk;
|
input clk;
|
| Line 350... |
Line 350... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
read <= 1'b0;
|
read <= 1'b0;
|
else
|
else
|
if (!last_cyc & wbm_cyc_o)
|
if (!last_cyc & wbm_cyc_o & !wbm_we_o)
|
read <= 1'b1;
|
read <= 1'b1;
|
else if (!waitrequest)
|
else if (!waitrequest)
|
read <= 1'b0;
|
read <= 1'b0;
|
|
|
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
|
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
|
| Line 365... |
Line 365... |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
|
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
counter <= 4'd0;
|
counter <= 4'd0;
|
write <= 1'b0;
|
|
end else
|
end else
|
if (!waitrequest & last_cyc & wbm_cyc_o) begin
|
if (wbm_we_o) begin
|
write <= 1'b1;
|
if (!waitrequest & !last_cyc & wbm_cyc_o) begin
|
counter <= burstcount -1;
|
counter <= burstcount -1;
|
end else if (waitrequest & last_cyc & wbm_cyc_o) begin
|
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
|
write <= 1'b1;
|
|
counter <= burstcount;
|
counter <= burstcount;
|
end else if (!waitrequst) begin
|
end else if (!waitrequest & wbm_stb_o) begin
|
counter <= counter - 4'd1;
|
counter <= counter - 4'd1;
|
write <= (counter!=4'd0 & wbm_stb_o)
|
|
end
|
end
|
|
end
|
|
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0;
|
|
|
`define MODULE wb3wb3_bridge
|
`define MODULE wb3wb3_bridge
|
`BASE`MODULE wbwb3inst (
|
`BASE`MODULE wbwb3inst (
|
`undef MODULE
|
`undef MODULE
|
// wishbone slave side
|
// wishbone slave side
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.