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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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| Rev 80 |
Rev 81 |
| Line 326... |
Line 326... |
input [31:0] readdata;
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input [31:0] readdata;
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output [31:0] writedata;
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output [31:0] writedata;
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output [31:2] address;
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output [31:2] address;
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output [3:0] be;
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output [3:0] be;
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output write;
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output write;
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output reg read;
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output read;
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output beginbursttransfer;
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output beginbursttransfer;
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output [3:0] burstcount;
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output [3:0] burstcount;
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input readdatavalid;
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input readdatavalid;
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input waitrequest;
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input waitrequest;
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input clk;
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input clk;
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| Line 346... |
Line 346... |
if (rst)
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if (rst)
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last_cyc <= 1'b0;
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last_cyc <= 1'b0;
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else
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else
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last_cyc <= wbm_cyc_o;
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last_cyc <= wbm_cyc_o;
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always @ (posedge clk or posedge rst)
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/*
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if (rst)
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always @ (posedge clk or posedge rst)
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read <= 1'b0;
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if (rst)
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else
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read <= 1'b0;
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if (!last_cyc & wbm_cyc_o & !wbm_we_o)
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else
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read <= 1'b1;
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if (!last_cyc & wbm_cyc_o & !wbm_we_o)
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else if (!waitrequest)
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read <= 1'b1;
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read <= 1'b0;
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else if (!waitrequest)
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read <= 1'b0;
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*/
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assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
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assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
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assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
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assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
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assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
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(wbm_bte_o==2'b10) ? 4'd8 :
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(wbm_bte_o==2'b10) ? 4'd8 :
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(wbm_bte_o==2'b11) ? 4'd16:
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(wbm_bte_o==2'b11) ? 4'd16:
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| Line 375... |
Line 378... |
counter <= burstcount;
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counter <= burstcount;
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end else if (!waitrequest & wbm_stb_o) begin
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end else if (!waitrequest & wbm_stb_o) begin
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counter <= counter - 4'd1;
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counter <= counter - 4'd1;
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end
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end
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end
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end
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assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0;
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assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
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`define MODULE wb3wb3_bridge
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`define MODULE wb3wb3_bridge
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`BASE`MODULE wbwb3inst (
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`BASE`MODULE wbwb3inst (
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`undef MODULE
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`undef MODULE
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// wishbone slave side
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// wishbone slave side
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