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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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| Rev 102 |
Rev 136 |
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VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v
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VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v
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INC_DIR = ./../../../rtl/verilog
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tb_wb_b3_ram_be:
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tb_wb_b3_ram_be:
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vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v
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vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v
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vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/sim/rtl_sim/run/wb_b3_ram_be.v
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vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/sim/rtl_sim/run/wb_b3_ram_be.v
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vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/bench/wbm.v
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vlog -reportprogress 300 -work work /home/michael/work/ocsvn/versatile_library/trunk/bench/wbm.v
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vlog -reportprogress 300 -work work ./wb_b3_dpram.v
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vlog -reportprogress 300 -work work ./wb_b3_dpram.v
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vlog -reportprogress 300 -work work ./../../../bench/wbm.v
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vlog -reportprogress 300 -work work ./../../../bench/wbm.v
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vlog -reportprogress 300 -work work ./../../../bench/tb_wb_b3_dpram.v
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vlog -reportprogress 300 -work work ./../../../bench/tb_wb_b3_dpram.v
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tb_wb_cache:
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tb_wb_cache:
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vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_CACHE +define+WB_RAM +define+RAM_BE $(VERILOG_FILES) > wb_cache.v
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vppreproc --noline --noblank +define+SYSTEMVERILOG +incdir+$(INC_DIR) +define+WB_AVALON_MEM_CACHE +define+WB_RAM +define+RAM_BE +define+WB_AVALON_MEM_CACHE $(VERILOG_FILES) > wb_cache.v
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vlog -reportprogress 300 -work work ./wb_cache.v
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vlog -reportprogress 300 -work work ./wb_cache.v
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vlog -reportprogress 300 -work work ./../../../bench/wbm.v
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vlog -reportprogress 300 -work work ./../../../bench/wbm.v
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vlog -reportprogress 300 -work work ./../../../bench/tb_wb_cache.v
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vlog -reportprogress 300 -work work ./../../../bench/tb_wb_cache.v
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