URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] [mt48lc16m16a2.v] - Diff between revs 9 and 106

Rev 9	Rev 106
Line 117...	Line 117...
`wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];`	`wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];`

`// Write Burst Mode`	`// Write Burst Mode`
`wire Write_burst_mode = Mode_reg[9];`	`wire Write_burst_mode = Mode_reg[9];`

`wire Debug = 1'b1; // Debug messages : 1 = On`	`wire Debug = 1'b0; // Debug messages : 1 = On`
`wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ`	`wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ`

`assign Dq = Dq_reg; // DQ buffer`	`assign Dq = Dq_reg; // DQ buffer`

`// Commands Operation`	`// Commands Operation`