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`include "tb_defines.v"
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//`include "tb_defines.v"
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module versatile_mem_ctrl_tb
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module versatile_mem_ctrl_tb
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(
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(
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output OK
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output OK
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);
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);
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|
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reg wb_clk, wb_rst;
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`ifdef NR_OF_WBM
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reg sdram_clk, sdram_rst;
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parameter nr_of_wbm = `NR_OF_WBM;
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reg tb_rst;
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`else
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parameter nr_of_wbm = 1;
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wire [31:0] wbm_dat_i [1:nr_of_wbm];
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`endif
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wire [3:0] wbm_sel_i [1:nr_of_wbm];
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wire [31:0] wbm_adr_i [1:nr_of_wbm];
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`ifdef SDRAM_CLK_PERIOD
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wire [2:0] wbm_cti_i [1:nr_of_wbm];
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parameter sdram_clk_period = `SDRAM_CLK_PERIOD;
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wire [1:0] wbm_bte_i [1:nr_of_wbm];
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`else
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wire wbm_cyc_i [1:nr_of_wbm];
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parameter sdram_clk_period = 8;
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wire wbm_stb_i [1:nr_of_wbm];
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`endif
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wire [31:0] wbm_dat_o [1:nr_of_wbm];
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wire wbm_ack_o [1:nr_of_wbm];
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`ifdef WB_CLK_PERIODS
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wire wbm_clk [1:nr_of_wbm];
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parameter [1:nr_of_wbm] wb_clk_periods = {`WB_CLK_PERIODS};
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wire wbm_rst;
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`else
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parameter [1:nr_of_wbm] wb_clk_periods = (20);
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`endif
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parameter wb_clk_period = 20;
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wire [31:0] wbm_a_dat_o [1:nr_of_wbm];
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wire [3:0] wbm_a_sel_o [1:nr_of_wbm];
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wire [31:0] wbm_a_adr_o [1:nr_of_wbm];
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wire [2:0] wbm_a_cti_o [1:nr_of_wbm];
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wire [1:0] wbm_a_bte_o [1:nr_of_wbm];
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wire wbm_a_we_o [1:nr_of_wbm];
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wire wbm_a_cyc_o [1:nr_of_wbm];
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wire wbm_a_stb_o [1:nr_of_wbm];
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wire [31:0] wbm_a_dat_i [1:nr_of_wbm];
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wire wbm_a_ack_i [1:nr_of_wbm];
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reg wbm_a_clk [1:nr_of_wbm];
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reg wbm_a_rst [1:nr_of_wbm];
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wire [31:0] wbm_b_dat_o [1:nr_of_wbm];
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wire [3:0] wbm_b_sel_o [1:nr_of_wbm];
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wire [31:2] wbm_b_adr_o [1:nr_of_wbm];
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wire [2:0] wbm_b_cti_o [1:nr_of_wbm];
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wire [1:0] wbm_b_bte_o [1:nr_of_wbm];
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wire wbm_b_we_o [1:nr_of_wbm];
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wire wbm_b_cyc_o [1:nr_of_wbm];
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wire wbm_b_stb_o [1:nr_of_wbm];
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wire [31:0] wbm_b_dat_i [1:nr_of_wbm];
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wire wbm_b_ack_i [1:nr_of_wbm];
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wire [31:0] wb_sdram_dat_i;
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wire [31:0] wb_sdram_dat_i;
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wire [3:0] wb_sdram_sel_i;
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wire [3:0] wb_sdram_sel_i;
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wire [31:0] wb_sdram_adr_i;
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wire [31:2] wb_sdram_adr_i;
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wire [2:0] wb_sdram_cti_i;
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wire [2:0] wb_sdram_cti_i;
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wire [1:0] wb_sdram_bte_i;
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wire [1:0] wb_sdram_bte_i;
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wire wb_sdram_we_i;
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wire wb_sdram_cyc_i;
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wire wb_sdram_cyc_i;
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wire wb_sdram_stb_i;
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wire wb_sdram_stb_i;
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wire [31:0] wb_sdram_dat_o;
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wire [31:0] wb_sdram_dat_o;
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wire wb_sdram_ack_o;
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wire wb_sdram_ack_o;
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reg wb_sdram_clk;
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reg wb_sdram_rst;
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wire [1:nr_of_wbm] wbm_OK;
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wire [1:0] ba, bad;
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genvar i;
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wire [12:0] a, ad;
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wire [15:0] dq_i;
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wire [15:0] dq_o;
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wire [15:0] dq_io;
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wire [1:0] dqs, dqs_n, dqs_i, dqs_o, dqs_n_i, dqs_n_o, dqs_io, dqs_n_io;
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wire [1:0] dqm, dqmd, dm_rdqs;
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wire dq_oe, dqs_oe;
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wire cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;
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wire ck_fb_i, ck_fb_o;
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`ifdef SDR_16 // SDR SDRAM
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`define DUT sdr_sdram_16_ctrl
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wb0 wb0i
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`define SDR 16
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(
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`ifdef SDR
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.adr(wb0_adr_i),
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wire [1:0] ba, ba_pad;
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.bte(wb0_bte_i),
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wire [12:0] a, a_pad;
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.cti(wb0_cti_i),
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wire [`SDR-1:0] dq_i, dq_o, dq_pad;
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.cyc(wb0_cyc_i),
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wire dq_oe;
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.dat(wb0_dat_i),
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wire [1:0] dqm, dqm_pad;
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.sel(wb0_sel_i),
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wire cke, cke_pad, cs_n, cs_n_pad, ras, ras_pad, cas, cas_pad, we, we_pad;
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.stb(wb0_stb_i),
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.we (wb0_we_i),
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assign #1 {ba_pad,a_pad} = {ba,a};
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.ack(wb0_ack_o),
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assign #1 {ras_pad, cas_pad, we_pad} = {ras,cas,we};
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.clk(wb_clk),
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assign #1 dqm_pad = dqm;
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.dat_i(wb0_dat_o),
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assign #1 cke_pad = cke;
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.reset(wb_rst)
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assign cs_n_pad = cs_n;
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);
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wb1 wb1i
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mt48lc16m16a2 mem(
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(
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.Dq(dq_pad),
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.adr(wb1_adr_i),
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.Addr(a_pad),
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.bte(wb1_bte_i),
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.Ba(ba_pad),
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.cti(wb1_cti_i),
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.Clk(wb_sdram_clk),
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.cyc(wb1_cyc_i),
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.Cke(cke_pad),
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.dat(wb1_dat_i),
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.Cs_n(cs_n_pad),
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.sel(wb1_sel_i),
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.Ras_n(ras_pad),
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.stb(wb1_stb_i),
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.Cas_n(cas_pad),
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.we (wb1_we_i),
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.We_n(we_pad),
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.ack(wb1_ack_o),
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.Dqm(dqm_pad));
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.clk(wb_clk),
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.dat_i(wb1_dat_o),
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assign #1 dq_pad = (dq_oe) ? dq_o : {`SDR{1'bz}};
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.reset(wb_rst)
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assign #1 dq_i = dq_pad;
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);
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wb4 wb4i
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`DUT DUT(
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(
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// wisbone i/f
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.adr(wb4_adr_i),
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.dat_i(wb_sdram_dat_i),
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.bte(wb4_bte_i),
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.adr_i({wb_sdram_adr_i[24:2],1'b0}),
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.cti(wb4_cti_i),
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.sel_i(wb_sdram_sel_i),
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.cyc(wb4_cyc_i),
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.cti_i(wb_sdram_cti_i),
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.dat(wb4_dat_i),
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.bte_i(wb_sdram_bte_i),
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.sel(wb4_sel_i),
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.we_i (wb_sdram_we_i),
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.stb(wb4_stb_i),
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.cyc_i(wb_sdram_cyc_i),
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.we (wb4_we_i),
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.stb_i(wb_sdram_stb_i),
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.ack(wb4_ack_o),
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.dat_o(wb_sdram_dat_o),
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.clk(wb_clk),
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.ack_o(wb_sdram_ack_o),
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.dat_i(wb4_dat_o),
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// SDR SDRAM
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.reset(wb_rst)
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.ba(ba),
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);
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.a(a),
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`endif
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.cmd({ras, cas, we}),
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.cke(cke),
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`ifdef DDR_16 // DDR2 SDRAM
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.cs_n(cs_n),
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wb0_ddr wb0i
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.dqm(dqm),
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(
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.adr(wb0_adr_i),
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.bte(wb0_bte_i),
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.cti(wb0_cti_i),
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.cyc(wb0_cyc_i),
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.dat(wb0_dat_i),
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.sel(wb0_sel_i),
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.stb(wb0_stb_i),
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.we (wb0_we_i),
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.ack(wb0_ack_o),
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.clk(wb_clk),
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.dat_i(wb0_dat_o),
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.reset(tb_rst)
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);
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wb1_ddr wb1i
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(
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.adr(wb1_adr_i),
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.bte(wb1_bte_i),
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.cti(wb1_cti_i),
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.cyc(wb1_cyc_i),
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.dat(wb1_dat_i),
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.sel(wb1_sel_i),
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.stb(wb1_stb_i),
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.we (wb1_we_i),
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.ack(wb1_ack_o),
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.clk(wb_clk),
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.dat_i(wb1_dat_o),
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.reset(tb_rst)
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);
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wb4_ddr wb4i
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(
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.adr(wb4_adr_i),
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.bte(wb4_bte_i),
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.cti(wb4_cti_i),
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.cyc(wb4_cyc_i),
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.dat(wb4_dat_i),
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.sel(wb4_sel_i),
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.stb(wb4_stb_i),
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.we (wb4_we_i),
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.ack(wb4_ack_o),
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.clk(wb_clk),
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.dat_i(wb4_dat_o),
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.reset(tb_rst)
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);
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`endif
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versatile_mem_ctrl_top # (
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.nr_of_wb_clk_domains(2),
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.nr_of_wb_ports_clk0(1),
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.nr_of_wb_ports_clk1(1),
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.nr_of_wb_ports_clk2(0),
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.nr_of_wb_ports_clk3(0))
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dut (
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.wb_adr_i_0({{wb0_adr_i[31:2],wb0_we_i,wb0_bte_i,wb0_cti_i},{wb1_adr_i[31:2],wb1_we_i,wb1_bte_i,wb1_cti_i}}),
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.wb_dat_i_0({{wb0_dat_i,wb0_sel_i},{wb1_dat_i,wb1_sel_i}}),
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.wb_dat_o_0({wb0_dat_o,wb1_dat_o}),
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.wb_stb_i_0({wb0_stb_i,wb1_stb_i}),
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.wb_cyc_i_0({wb0_cyc_i,wb1_cyc_i}),
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.wb_ack_o_0({wb0_ack_o,wb1_ack_o}),
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.wb_adr_i_1({wb4_adr_i[31:2],wb4_we_i,wb4_bte_i,wb4_cti_i}),
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.wb_dat_i_1({wb4_dat_i,wb4_sel_i}),
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.wb_dat_o_1(wb4_dat_o),
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.wb_stb_i_1(wb4_stb_i),
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.wb_cyc_i_1(wb4_cyc_i),
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.wb_ack_o_1(wb4_ack_o),
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.wb_adr_i_2(2'b0),
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.wb_dat_i_2(2'b0),
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.wb_dat_o_2(),
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.wb_stb_i_2(2'b0),
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.wb_cyc_i_2(2'b0),
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.wb_ack_o_2(),
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.wb_adr_i_3(2'b0),
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.wb_dat_i_3(2'b0),
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.wb_dat_o_3(),
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.wb_stb_i_3(2'b0),
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.wb_cyc_i_3(2'b0),
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.wb_ack_o_3(),
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// SDR SDRAM 16
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`ifdef SDR_16
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.ba_pad_o(ba),
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.a_pad_o(a),
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.cs_n_pad_o(cs_n),
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.ras_pad_o(ras),
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.cas_pad_o(cas),
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.we_pad_o(we),
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.dq_o(dq_o),
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.dqm_pad_o(dqm),
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.dq_i(dq_i),
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.dq_i(dq_i),
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.dq_o(dq_o),
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.dq_oe(dq_oe),
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.dq_oe(dq_oe),
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.cke_pad_o(cke),
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// system
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`endif
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.clk(wb_sdram_clk), .rst(wb_sdram_rst));
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`ifdef DDR_16
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// DDR2 SDRAM 16
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.ck_pad_o(ck),
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.ck_n_pad_o(ck_n),
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.cke_pad_o(cke),
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.ck_fb_pad_o(ck_fb_o),
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.ck_fb_pad_i(ck_fb_i),
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.cs_n_pad_o(cs_n),
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.ras_pad_o(ras),
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.cas_pad_o(cas),
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.we_pad_o(we),
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.dm_rdqs_pad_io(dm_rdqs),
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.ba_pad_o(ba),
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.addr_pad_o(a),
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.dq_pad_io(dq_io),
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.dqs_pad_io(dqs_io),
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.dqs_oe(dqs_oe),
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.dqs_n_pad_io(dqs_n_io),
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.rdqs_n_pad_i(),
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.odt_pad_o(),
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`endif
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// misc
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.wb_clk({wb_clk,wb_clk}),
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.wb_rst({wb_rst,wb_rst}),
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.sdram_clk(sdram_clk),
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.sdram_rst(wb_rst)
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);
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`ifdef SDR_16
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assign #1 dq_io = dq_oe ? dq_o : {16{1'bz}};
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assign #1 dq_i = dq_io;
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assign #1 dqmd = dqm;
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assign #1 dqs_io = dqs_oe ? dqs_o : {2{1'bz}};
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assign #1 dqs_i = dqs_io;
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assign #1 dqs_n_io = dqs_oe ? dqs_n_o : {2{1'bz}};
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assign #1 dqs_n_i = dqs_n_io;
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`endif
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`endif
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`ifdef DDR_16
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// wishbone master(s)
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assign #1 dqmd = dqm;
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generate
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assign ck_fb_i = ck_fb_o;
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for (i=1; i <= nr_of_wbm; i=i+1) begin: wb_master
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`endif
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wbm wbmi(
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.adr_o(wbm_a_adr_o[i]),
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.bte_o(wbm_a_bte_o[i]),
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.cti_o(wbm_a_cti_o[i]),
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.dat_o(wbm_a_dat_o[i]),
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.sel_o(wbm_a_sel_o[i]),
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.we_o (wbm_a_we_o[i]),
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.cyc_o(wbm_a_cyc_o[i]),
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.stb_o(wbm_a_stb_o[i]),
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.dat_i(wbm_a_dat_i[i]),
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.ack_i(wbm_a_ack_i[i]),
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.clk(wbm_a_clk[i]),
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.reset(wbm_a_rst[i]),
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.OK(wbm_OK[i])
|
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);
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wb3wb3_bridge wbwb_bridgei (
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// wishbone slave side
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.wbs_dat_i(wbm_a_dat_o[i]),
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.wbs_adr_i(wbm_a_adr_o[i][31:2]),
|
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.wbs_sel_i(wbm_a_sel_o[i]),
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.wbs_bte_i(wbm_a_bte_o[i]),
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.wbs_cti_i(wbm_a_cti_o[i]),
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.wbs_we_i (wbm_a_we_o[i]),
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.wbs_cyc_i(wbm_a_cyc_o[i]),
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.wbs_stb_i(wbm_a_stb_o[i]),
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.wbs_dat_o(wbm_a_dat_i[i]),
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.wbs_ack_o(wbm_a_ack_i[i]),
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.wbs_clk(wbm_a_clk[i]),
|
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.wbs_rst(wbm_a_rst[i]),
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// wishbone master side
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.wbm_dat_o(wbm_b_dat_o[i]),
|
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.wbm_adr_o(wbm_b_adr_o[i]),
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.wbm_sel_o(wbm_b_sel_o[i]),
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.wbm_bte_o(wbm_b_bte_o[i]),
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.wbm_cti_o(wbm_b_cti_o[i]),
|
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.wbm_we_o (wbm_b_we_o[i]),
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.wbm_cyc_o(wbm_b_cyc_o[i]),
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.wbm_stb_o(wbm_b_stb_o[i]),
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.wbm_dat_i(wbm_b_dat_i[i]),
|
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.wbm_ack_i(wbm_b_ack_i[i]),
|
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.wbm_clk(wb_sdram_clk),
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.wbm_rst(wb_sdram_rst));
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|
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assign #1 ad = a;
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end
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assign #1 bad = ba;
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endgenerate
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assign #1 cked = cke;
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assign #1 cs_nd = cs_n;
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assign #1 rasd = ras;
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assign #1 casd = cas;
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assign #1 wed = we;
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|
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`ifdef SDR_16 // SDR SDRAM Simulation model
|
`define SINGLE_WB
|
mt48lc16m16a2 sdram
|
`ifdef SINGLE_WB
|
(
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assign wb_sdram_dat_i=wbm_b_dat_o[1];
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.Dq(dq_io),
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assign wb_sdram_sel_i=wbm_b_sel_o[1];
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.Addr(ad),
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assign wb_sdram_adr_i=wbm_b_adr_o[1];
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.Ba(bad),
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assign wb_sdram_we_i =wbm_b_we_o[1];
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.Clk(sdram_clk),
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assign wb_sdram_bte_i=wbm_b_bte_o[1];
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.Cke(cked),
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assign wb_sdram_cti_i=wbm_b_cti_o[1];
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.Cs_n(cs_nd),
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assign wb_sdram_cyc_i=wbm_b_cyc_o[1];
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.Ras_n(rasd),
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assign wb_sdram_stb_i=wbm_b_stb_o[1];
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.Cas_n(casd),
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assign wbm_b_dat_i[1]=wb_sdram_dat_o;
|
.We_n(wed),
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assign wbm_b_ack_i[1]=wb_sdram_ack_o;
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.Dqm(dqmd)
|
|
);
|
|
`endif
|
|
`ifdef DDR_16 // DDR2 SDRAM Simulation model
|
|
ddr2 ddr2_sdram
|
|
(
|
|
.ck(ck),
|
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.ck_n(ck_n),
|
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.cke(cke),
|
|
.cs_n(cs_n),
|
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.ras_n(ras),
|
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.cas_n(cas),
|
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.we_n(we),
|
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.dm_rdqs(dm_rdqs),
|
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.ba(ba),
|
|
.addr(a),
|
|
.dq(dq_io),
|
|
.dqs(dqs_io),
|
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.dqs_n(dqs_n_io),
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.rdqs_n(),
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.odt()
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|
);
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`endif
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`endif
|
|
|
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assign OK = &wbm_OK;
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|
|
|
|
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generate
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for (i=1; i <= nr_of_wbm; i=i+1) begin: wb_reset
|
|
|
// Wishbone reset
|
// Wishbone reset
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initial
|
initial
|
begin
|
begin
|
#0 wb_rst = 1'b1;
|
#0 wbm_a_rst[i] = 1'b1;
|
#200 wb_rst = 1'b1;
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#200 wbm_a_rst[i] = 1'b0;
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#200000 wb_rst = 1'b0;
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|
end
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end
|
|
|
// SDRAM reset
|
// Wishbone clock
|
initial
|
initial
|
begin
|
begin
|
#0 sdram_rst = 1'b1;
|
#0 wbm_a_clk[i] = 1'b0;
|
#200 sdram_rst = 1'b1;
|
forever
|
#200000 sdram_rst = 1'b0;
|
#(wb_clk_period/2) wbm_a_clk[i] = !wbm_a_clk[i];
|
end
|
end
|
|
|
// Test bench reset
|
|
initial
|
|
begin
|
|
#0 tb_rst = 1'b1;
|
|
#200 tb_rst = 1'b1;
|
|
//#200000 tb_rst = 1'b0;
|
|
#300000 tb_rst = 1'b0; // hold reset to let initialization complete
|
|
end
|
end
|
|
endgenerate
|
|
|
// Wishbone clock
|
// SDRAM reset
|
initial
|
initial
|
begin
|
begin
|
#0 wb_clk = 1'b0;
|
#0 wb_sdram_rst = 1'b1;
|
forever
|
#200 wb_sdram_rst = 1'b0;
|
#(wb0_clk_period/2) wb_clk = !wb_clk;
|
|
end
|
end
|
|
|
// SDRAM clock
|
// SDRAM clock
|
initial
|
initial
|
begin
|
begin
|
#0 sdram_clk = 1'b0;
|
#0 wb_sdram_clk = 1'b0;
|
forever
|
forever
|
#(sdram_clk_period/2) sdram_clk = !sdram_clk;
|
#(sdram_clk_period/2) wb_sdram_clk = !wb_sdram_clk;
|
end
|
end
|
|
|
endmodule // versatile_mem_ctrl_tb
|
endmodule // versatile_mem_ctrl_tb
|
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No newline at end of file
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No newline at end of file
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