| Line 22... |
Line 22... |
`else
|
`else
|
parameter [1:nr_of_wbm] wb_clk_periods = (20);
|
parameter [1:nr_of_wbm] wb_clk_periods = (20);
|
`endif
|
`endif
|
parameter wb_clk_period = 20;
|
parameter wb_clk_period = 20;
|
|
|
wire [31:0] wbm_a_dat_o [1:nr_of_wbm];
|
wire [31:0] wbm_a_dat_o;
|
wire [3:0] wbm_a_sel_o [1:nr_of_wbm];
|
wire [3:0] wbm_a_sel_o;
|
wire [31:0] wbm_a_adr_o [1:nr_of_wbm];
|
wire [31:0] wbm_a_adr_o;
|
wire [2:0] wbm_a_cti_o [1:nr_of_wbm];
|
wire [2:0] wbm_a_cti_o;
|
wire [1:0] wbm_a_bte_o [1:nr_of_wbm];
|
wire [1:0] wbm_a_bte_o;
|
wire wbm_a_we_o [1:nr_of_wbm];
|
wire wbm_a_we_o ;
|
wire wbm_a_cyc_o [1:nr_of_wbm];
|
wire wbm_a_cyc_o;
|
wire wbm_a_stb_o [1:nr_of_wbm];
|
wire wbm_a_stb_o;
|
wire [31:0] wbm_a_dat_i [1:nr_of_wbm];
|
wire [31:0] wbm_a_dat_i;
|
wire wbm_a_ack_i [1:nr_of_wbm];
|
wire wbm_a_ack_i;
|
reg wbm_a_clk [1:nr_of_wbm];
|
reg wbm_a_clk ;
|
reg wbm_a_rst [1:nr_of_wbm];
|
reg wbm_a_rst ;
|
|
|
wire [31:0] wbm_b_dat_o [1:nr_of_wbm];
|
wire [31:0] wbm_b_dat_o;
|
wire [3:0] wbm_b_sel_o [1:nr_of_wbm];
|
wire [3:0] wbm_b_sel_o;
|
wire [31:2] wbm_b_adr_o [1:nr_of_wbm];
|
wire [31:2] wbm_b_adr_o;
|
wire [2:0] wbm_b_cti_o [1:nr_of_wbm];
|
wire [2:0] wbm_b_cti_o;
|
wire [1:0] wbm_b_bte_o [1:nr_of_wbm];
|
wire [1:0] wbm_b_bte_o;
|
wire wbm_b_we_o [1:nr_of_wbm];
|
wire wbm_b_we_o ;
|
wire wbm_b_cyc_o [1:nr_of_wbm];
|
wire wbm_b_cyc_o;
|
wire wbm_b_stb_o [1:nr_of_wbm];
|
wire wbm_b_stb_o;
|
wire [31:0] wbm_b_dat_i [1:nr_of_wbm];
|
wire [31:0] wbm_b_dat_i;
|
wire wbm_b_ack_i [1:nr_of_wbm];
|
wire wbm_b_ack_i;
|
|
|
wire [31:0] wb_sdram_dat_i;
|
wire [31:0] wb_sdram_dat_i;
|
wire [3:0] wb_sdram_sel_i;
|
wire [3:0] wb_sdram_sel_i;
|
wire [31:2] wb_sdram_adr_i;
|
wire [31:2] wb_sdram_adr_i;
|
wire [2:0] wb_sdram_cti_i;
|
wire [2:0] wb_sdram_cti_i;
|
| Line 59... |
Line 59... |
wire [31:0] wb_sdram_dat_o;
|
wire [31:0] wb_sdram_dat_o;
|
wire wb_sdram_ack_o;
|
wire wb_sdram_ack_o;
|
reg wb_sdram_clk;
|
reg wb_sdram_clk;
|
reg wb_sdram_rst;
|
reg wb_sdram_rst;
|
|
|
wire [1:nr_of_wbm] wbm_OK;
|
wire wbm_OK;
|
|
|
genvar i;
|
genvar i;
|
|
|
`define DUT sdr_sdram_16_ctrl
|
`define DUT sdr_sdram_16_ctrl
|
`define SDR 16
|
`define SDR 16
|
| Line 73... |
Line 73... |
wire [`SDR-1:0] dq_i, dq_o, dq_pad;
|
wire [`SDR-1:0] dq_i, dq_o, dq_pad;
|
wire dq_oe;
|
wire dq_oe;
|
wire [1:0] dqm, dqm_pad;
|
wire [1:0] dqm, dqm_pad;
|
wire cke, cke_pad, cs_n, cs_n_pad, ras, ras_pad, cas, cas_pad, we, we_pad;
|
wire cke, cke_pad, cs_n, cs_n_pad, ras, ras_pad, cas, cas_pad, we, we_pad;
|
|
|
assign #1 {ba_pad,a_pad} = {ba,a};
|
vl_o_dff # ( .width(20), .reset_value({2'b00, 13'h0,3'b111,2'b11})) o0(
|
assign #1 {ras_pad, cas_pad, we_pad} = {ras,cas,we};
|
.d_i({ba,a,ras,cas,we,dqm}),
|
assign #1 dqm_pad = dqm;
|
.o_pad({ba_pad,a_pad,ras_pad, cas_pad, we_pad, dqm_pad}),
|
|
.clk(wb_sdram_clk),
|
|
.rst(wb_sdram_rst));
|
|
/*
|
|
assign #1 {ba_pad,a_pad} = {ba,a};
|
|
assign #1 {ras_pad, cas_pad, we_pad} = {ras,cas,we};
|
|
assign #1 dqm_pad = dqm;*/
|
assign #1 cke_pad = cke;
|
assign #1 cke_pad = cke;
|
assign cs_n_pad = cs_n;
|
assign cs_n_pad = cs_n;
|
|
vl_io_dff_oe # ( .width(16)) io0 (
|
|
.d_i(dq_i),
|
|
.d_o(dq_o),
|
|
.oe(dq_oe),
|
|
.io_pad(dq_pad),
|
|
.clk(wb_sdram_clk),
|
|
.rst(wb_sdram_rst));
|
|
|
mt48lc16m16a2 mem(
|
mt48lc16m16a2 mem(
|
.Dq(dq_pad),
|
.Dq(dq_pad),
|
.Addr(a_pad),
|
.Addr(a_pad),
|
.Ba(ba_pad),
|
.Ba(ba_pad),
|
| Line 91... |
Line 104... |
.Ras_n(ras_pad),
|
.Ras_n(ras_pad),
|
.Cas_n(cas_pad),
|
.Cas_n(cas_pad),
|
.We_n(we_pad),
|
.We_n(we_pad),
|
.Dqm(dqm_pad));
|
.Dqm(dqm_pad));
|
|
|
assign #1 dq_pad = (dq_oe) ? dq_o : {`SDR{1'bz}};
|
`DUT
|
assign #1 dq_i = dq_pad;
|
# (.tRFC(9), .cl(3))
|
|
DUT(
|
`DUT DUT(
|
|
// wisbone i/f
|
// wisbone i/f
|
.dat_i(wb_sdram_dat_i),
|
.dat_i(wbm_b_dat_o),
|
.adr_i({wb_sdram_adr_i[24:2],1'b0}),
|
.adr_i({wbm_b_adr_o[24:2],1'b0}),
|
.sel_i(wb_sdram_sel_i),
|
.sel_i(wbm_b_sel_o),
|
.cti_i(wb_sdram_cti_i),
|
`ifndef NO_BURST
|
.bte_i(wb_sdram_bte_i),
|
.bte_i(wbm_b_bte_o),
|
.we_i (wb_sdram_we_i),
|
`endif
|
.cyc_i(wb_sdram_cyc_i),
|
.we_i (wbm_b_we_o),
|
.stb_i(wb_sdram_stb_i),
|
.cyc_i(wbm_b_cyc_o),
|
.dat_o(wb_sdram_dat_o),
|
.stb_i(wbm_b_stb_o),
|
.ack_o(wb_sdram_ack_o),
|
.dat_o(wbm_b_dat_i),
|
|
.ack_o(wbm_b_ack_i),
|
// SDR SDRAM
|
// SDR SDRAM
|
.ba(ba),
|
.ba(ba),
|
.a(a),
|
.a(a),
|
.cmd({ras, cas, we}),
|
.cmd({ras, cas, we}),
|
.cke(cke),
|
.cke(cke),
|
| Line 121... |
Line 134... |
// system
|
// system
|
.clk(wb_sdram_clk), .rst(wb_sdram_rst));
|
.clk(wb_sdram_clk), .rst(wb_sdram_rst));
|
|
|
`endif
|
`endif
|
|
|
// wishbone master(s)
|
// wishbone master
|
generate
|
|
for (i=1; i <= nr_of_wbm; i=i+1) begin: wb_master
|
|
|
|
wbm wbmi(
|
wbm wbmi(
|
.adr_o(wbm_a_adr_o[i]),
|
.adr_o(wbm_a_adr_o),
|
.bte_o(wbm_a_bte_o[i]),
|
.bte_o(wbm_a_bte_o),
|
.cti_o(wbm_a_cti_o[i]),
|
.cti_o(wbm_a_cti_o),
|
.dat_o(wbm_a_dat_o[i]),
|
.dat_o(wbm_a_dat_o),
|
.sel_o(wbm_a_sel_o[i]),
|
.sel_o(wbm_a_sel_o),
|
.we_o (wbm_a_we_o[i]),
|
.we_o (wbm_a_we_o),
|
.cyc_o(wbm_a_cyc_o[i]),
|
.cyc_o(wbm_a_cyc_o),
|
.stb_o(wbm_a_stb_o[i]),
|
.stb_o(wbm_a_stb_o),
|
.dat_i(wbm_a_dat_i[i]),
|
.dat_i(wbm_a_dat_i),
|
.ack_i(wbm_a_ack_i[i]),
|
.ack_i(wbm_a_ack_i),
|
.clk(wbm_a_clk[i]),
|
.clk(wbm_a_clk),
|
.reset(wbm_a_rst[i]),
|
.reset(wbm_a_rst),
|
.OK(wbm_OK[i])
|
.OK(wbm_OK)
|
);
|
);
|
|
|
wb3wb3_bridge wbwb_bridgei (
|
vl_wb3wb3_bridge wbwb_bridgei (
|
// wishbone slave side
|
// wishbone slave side
|
.wbs_dat_i(wbm_a_dat_o[i]),
|
.wbs_dat_i(wbm_a_dat_o),
|
.wbs_adr_i(wbm_a_adr_o[i][31:2]),
|
.wbs_adr_i(wbm_a_adr_o[31:2]),
|
.wbs_sel_i(wbm_a_sel_o[i]),
|
.wbs_sel_i(wbm_a_sel_o),
|
.wbs_bte_i(wbm_a_bte_o[i]),
|
.wbs_bte_i(wbm_a_bte_o),
|
.wbs_cti_i(wbm_a_cti_o[i]),
|
.wbs_cti_i(wbm_a_cti_o),
|
.wbs_we_i (wbm_a_we_o[i]),
|
.wbs_we_i (wbm_a_we_o),
|
.wbs_cyc_i(wbm_a_cyc_o[i]),
|
.wbs_cyc_i(wbm_a_cyc_o),
|
.wbs_stb_i(wbm_a_stb_o[i]),
|
.wbs_stb_i(wbm_a_stb_o),
|
.wbs_dat_o(wbm_a_dat_i[i]),
|
.wbs_dat_o(wbm_a_dat_i),
|
.wbs_ack_o(wbm_a_ack_i[i]),
|
.wbs_ack_o(wbm_a_ack_i),
|
.wbs_clk(wbm_a_clk[i]),
|
.wbs_clk(wbm_a_clk),
|
.wbs_rst(wbm_a_rst[i]),
|
.wbs_rst(wbm_a_rst),
|
// wishbone master side
|
// wishbone master side
|
.wbm_dat_o(wbm_b_dat_o[i]),
|
.wbm_dat_o(wbm_b_dat_o),
|
.wbm_adr_o(wbm_b_adr_o[i]),
|
.wbm_adr_o(wbm_b_adr_o),
|
.wbm_sel_o(wbm_b_sel_o[i]),
|
.wbm_sel_o(wbm_b_sel_o),
|
.wbm_bte_o(wbm_b_bte_o[i]),
|
.wbm_bte_o(wbm_b_bte_o),
|
.wbm_cti_o(wbm_b_cti_o[i]),
|
.wbm_cti_o(wbm_b_cti_o),
|
.wbm_we_o (wbm_b_we_o[i]),
|
.wbm_we_o (wbm_b_we_o),
|
.wbm_cyc_o(wbm_b_cyc_o[i]),
|
.wbm_cyc_o(wbm_b_cyc_o),
|
.wbm_stb_o(wbm_b_stb_o[i]),
|
.wbm_stb_o(wbm_b_stb_o),
|
.wbm_dat_i(wbm_b_dat_i[i]),
|
.wbm_dat_i(wbm_b_dat_i),
|
.wbm_ack_i(wbm_b_ack_i[i]),
|
.wbm_ack_i(wbm_b_ack_i),
|
.wbm_clk(wb_sdram_clk),
|
.wbm_clk(wb_sdram_clk),
|
.wbm_rst(wb_sdram_rst));
|
.wbm_rst(wb_sdram_rst));
|
|
|
end
|
|
endgenerate
|
|
|
|
`define SINGLE_WB
|
|
`ifdef SINGLE_WB
|
|
assign wb_sdram_dat_i=wbm_b_dat_o[1];
|
|
assign wb_sdram_sel_i=wbm_b_sel_o[1];
|
|
assign wb_sdram_adr_i=wbm_b_adr_o[1];
|
|
assign wb_sdram_we_i =wbm_b_we_o[1];
|
|
assign wb_sdram_bte_i=wbm_b_bte_o[1];
|
|
assign wb_sdram_cti_i=wbm_b_cti_o[1];
|
|
assign wb_sdram_cyc_i=wbm_b_cyc_o[1];
|
|
assign wb_sdram_stb_i=wbm_b_stb_o[1];
|
|
assign wbm_b_dat_i[1]=wb_sdram_dat_o;
|
|
assign wbm_b_ack_i[1]=wb_sdram_ack_o;
|
|
`endif
|
|
|
|
assign OK = &wbm_OK;
|
|
|
|
|
assign OK = wbm_OK;
|
|
|
generate
|
|
for (i=1; i <= nr_of_wbm; i=i+1) begin: wb_reset
|
|
|
|
// Wishbone reset
|
// Wishbone reset
|
initial
|
initial
|
begin
|
begin
|
#0 wbm_a_rst[i] = 1'b1;
|
#0 wbm_a_rst = 1'b1;
|
#200 wbm_a_rst[i] = 1'b0;
|
#200 wbm_a_rst = 1'b0;
|
end
|
end
|
|
|
// Wishbone clock
|
// Wishbone clock
|
initial
|
initial
|
begin
|
begin
|
#0 wbm_a_clk[i] = 1'b0;
|
#0 wbm_a_clk = 1'b0;
|
forever
|
forever
|
#(wb_clk_period/2) wbm_a_clk[i] = !wbm_a_clk[i];
|
#(wb_clk_period/2) wbm_a_clk = !wbm_a_clk;
|
end
|
end
|
|
|
|
|
end
|
|
endgenerate
|
|
|
|
// SDRAM reset
|
// SDRAM reset
|
initial
|
initial
|
begin
|
begin
|
#0 wb_sdram_rst = 1'b1;
|
#0 wb_sdram_rst = 1'b1;
|
