Subversion Repositories versatile_mem_ctrl

   wire [15:0] dq_io;

   wire [15:0] dq_io;

   wire [1:0]  dqs, dqs_n, dqs_i, dqs_o, dqs_n_i, dqs_n_o, dqs_io, dqs_n_io;

   wire [1:0]  dqs, dqs_n, dqs_i, dqs_o, dqs_n_i, dqs_n_o, dqs_io, dqs_n_io;

   wire [1:0]  dqm, dqmd, dm_rdqs;

   wire [1:0]  dqm, dqmd, dm_rdqs;

   wire        dq_oe, dqs_oe;

   wire        dq_oe, dqs_oe;

   wire        cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;

   wire        cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;

`ifdef SDR_16

`ifdef SDR_16

   wb0 wb0i

   wb0 wb0i

     (

     (

      .adr(wb0_adr_i),

      .adr(wb0_adr_i),

   assign #1 dqmd = dqm;

   assign #1 dqmd = dqm;

   assign #1 dqs_io = dqs_oe ? dqs_o : {2{1'bz}};

   assign #1 dqs_io = dqs_oe ? dqs_o : {2{1'bz}};

   assign #1 dqs_i  = dqs_io;

   assign #1 dqs_i  = dqs_io;

   assign #1 dqs_n_io = dqs_oe ? dqs_n_o : {2{1'bz}};

   assign #1 dqs_n_io = dqs_oe ? dqs_n_o : {2{1'bz}};

   assign #1 dqs_n_i  = dqs_n_io;

   assign #1 dqs_n_i  = dqs_n_io;

`endif

`endif

`ifdef DDR_16

`ifdef DDR_16

   assign #1 dqmd = dqm;

   assign #1 dqmd = dqm;

`endif

`endif

   assign #1 ad = a;

   assign #1 ad = a;

   assign #1 bad = ba;

   assign #1 bad = ba;

   assign #1 cked = cke;

   assign #1 cked = cke;