URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] [tb.v] - Diff between revs 14 and 15

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Rev 14	Rev 15
Line 46...	Line 46...
`wire [1:0] dqm, dqmd, dm_rdqs;`	`wire [1:0] dqm, dqmd, dm_rdqs;`
`wire dq_oe, dqs_oe;`	`wire dq_oe, dqs_oe;`
`wire cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;`	`wire cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;`
`wire ck_fb_i, ck_fb_o;`	`wire ck_fb_i, ck_fb_o;`

`ifdef SDR_16	`ifdef SDR_16 // SDR SDRAM
`wb0 wb0i`	`wb0 wb0i`
`(`	`(`
`.adr(wb0_adr_i),`	`.adr(wb0_adr_i),`
`.bte(wb0_bte_i),`	`.bte(wb0_bte_i),`
`.cti(wb0_cti_i),`	`.cti(wb0_cti_i),`
Line 94...	Line 94...
`.dat_i(wb4_dat_o),`	`.dat_i(wb4_dat_o),`
`.reset(wb_rst)`	`.reset(wb_rst)`
`);`	`);`
`endif	`endif

`ifdef DDR_16	`ifdef DDR_16 // DDR2 SDRAM
`wb0_ddr wb0i`	`wb0_ddr wb0i`
`(`	`(`
`.adr(wb0_adr_i),`	`.adr(wb0_adr_i),`
`.bte(wb0_bte_i),`	`.bte(wb0_bte_i),`
`.cti(wb0_cti_i),`	`.cti(wb0_cti_i),`
Line 199...	Line 199...
`.ck_fb_pad_i(ck_fb_i),`	`.ck_fb_pad_i(ck_fb_i),`
`.cs_n_pad_o(cs_n),`	`.cs_n_pad_o(cs_n),`
`.ras_pad_o(ras),`	`.ras_pad_o(ras),`
`.cas_pad_o(cas),`	`.cas_pad_o(cas),`
`.we_pad_o(we),`	`.we_pad_o(we),`
`.dm_rdqs_i(),`	`.dm_rdqs_pad_io(dm_rdqs),`
`.dm_rdqs_o(dm_rdqs),`
`.ba_pad_o(ba),`	`.ba_pad_o(ba),`
`.addr_pad_o(a),`	`.addr_pad_o(a),`
`//.dq_i(dq_i),`
`//.dq_o(dq_o),`
`.dq_pad_io(dq_io),`	`.dq_pad_io(dq_io),`
`//.dq_oe(dq_oe),`
`//.dqs_i(dqs_i),`
`//.dqs_o(dqs_o),`
`.dqs_pad_io(dqs_io),`	`.dqs_pad_io(dqs_io),`
`.dqs_oe(dqs_oe),`	`.dqs_oe(dqs_oe),`
`//.dqs_n_i(dqs_n_i),`
`//.dqs_n_o(dqs_n_o),`
`.dqs_n_pad_io(dqs_n_io),`	`.dqs_n_pad_io(dqs_n_io),`
`.rdqs_n_pad_i(),`	`.rdqs_n_pad_i(),`
`.odt_pad_o(),`	`.odt_pad_o(),`
`endif	`endif
`// misc`	`// misc`
Line 235...	Line 227...
`assign #1 dqs_n_i = dqs_n_io;`	`assign #1 dqs_n_i = dqs_n_io;`
`endif	`endif

`ifdef DDR_16	`ifdef DDR_16
`assign #1 dqmd = dqm;`	`assign #1 dqmd = dqm;`
`assign #1 ck_fb_i = ck_fb_o;`	`assign ck_fb_i = ck_fb_o;`
`endif	`endif

`assign #1 ad = a;`	`assign #1 ad = a;`
`assign #1 bad = ba;`	`assign #1 bad = ba;`
`assign #1 cked = cke;`	`assign #1 cked = cke;`
`assign #1 cs_nd = cs_n;`	`assign #1 cs_nd = cs_n;`
`assign #1 rasd = ras;`	`assign #1 rasd = ras;`
`assign #1 casd = cas;`	`assign #1 casd = cas;`
`assign #1 wed = we;`	`assign #1 wed = we;`

`ifdef SDR_16	`ifdef SDR_16 // SDR SDRAM Simulation model
`mt48lc16m16a2 sdram`	`mt48lc16m16a2 sdram`
`(`	`(`
`.Dq(dq_io),`	`.Dq(dq_io),`
`.Addr(ad),`	`.Addr(ad),`
`.Ba(bad),`	`.Ba(bad),`
Line 261...	Line 253...
`.Cas_n(casd),`	`.Cas_n(casd),`
`.We_n(wed),`	`.We_n(wed),`
`.Dqm(dqmd)`	`.Dqm(dqmd)`
`);`	`);`
`endif	`endif
`ifdef DDR_16	`ifdef DDR_16 // DDR2 SDRAM Simulation model
`ddr2 ddr2_sdram`	`ddr2 ddr2_sdram`
`(`	`(`
`.ck(ck),`	`.ck(ck),`
`.ck_n(ck_n),`	`.ck_n(ck_n),`
`.cke(cke),`	`.cke(cke),`
Line 286...	Line 278...

`initial`	`initial`
`begin`	`begin`
`#0 wb_rst = 1'b1;`	`#0 wb_rst = 1'b1;`
`#200 wb_rst = 1'b1;`	`#200 wb_rst = 1'b1;`
`#400 wb_rst = 1'b0;`	`#200000 wb_rst = 1'b0;`
`end`	`end`

`initial`	`initial`
`begin`	`begin`
`#0 wb_clk = 1'b0;`	`#0 wb_clk = 1'b0;`

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[/] [versatile_mem_ctrl/] [trunk/] [bench/] [tb.v] - Diff between revs 14 and 15