| Line 3... |
Line 3... |
module versatile_mem_ctrl_tb
|
module versatile_mem_ctrl_tb
|
(
|
(
|
output OK
|
output OK
|
);
|
);
|
|
|
|
// number of wb clock domains
|
|
parameter nr_of_wb_clk_domains = 1;
|
|
// number of wb ports in each wb clock domain
|
|
parameter nr_of_wb_ports_clk0 = 3;
|
|
parameter nr_of_wb_ports_clk1 = 0;
|
|
parameter nr_of_wb_ports_clk2 = 0;
|
|
parameter nr_of_wb_ports_clk3 = 0;
|
|
|
reg sdram_clk, wb_clk, wb_rst;
|
reg sdram_clk, wb_clk, wb_rst;
|
|
|
wire [31:0] wb0_dat_i;
|
wire [31:0] wb0_dat_i;
|
wire [3:0] wb0_sel_i;
|
wire [3:0] wb0_sel_i;
|
wire [31:0] wb0_adr_i;
|
wire [31:0] wb0_adr_i;
|
| Line 46... |
Line 54... |
wire [1:0] dqm, dqmd, dm_rdqs;
|
wire [1:0] dqm, dqmd, dm_rdqs;
|
wire dq_oe, dqs_oe;
|
wire dq_oe, dqs_oe;
|
wire cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;
|
wire cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;
|
wire ck_fb_i, ck_fb_o;
|
wire ck_fb_i, ck_fb_o;
|
|
|
|
//
|
|
wire [36*nr_of_wb_ports_clk0-1:0] wb_dat_i_v;
|
|
wire [36*nr_of_wb_ports_clk0-1:0] wb_adr_i_v;
|
|
wire [31:0] wb_dat_o_v;
|
|
wire [0:nr_of_wb_ports_clk0-1] wb_cyc_i_v;
|
|
wire [0:nr_of_wb_ports_clk0-1] wb_stb_i_v;
|
|
wire [0:nr_of_wb_ports_clk0-1] wb_ack_o_v;
|
|
//
|
|
assign wb_dat_i_v = {4'h0,wb4_dat_i,4'h0,wb1_dat_i,3'h0,wb0_dat_i};
|
|
assign wb_adr_i_v = {4'h0,wb4_adr_i,4'h0,wb1_adr_i,3'h0,wb0_adr_i};
|
|
assign wb_cyc_i_v = {wb4_cyc_i,wb1_cyc_i,wb0_cyc_i};
|
|
assign wb_stb_i_v = {wb4_stb_i,wb1_stb_i,wb0_stb_i};
|
|
assign wb_ack_o_v = {};
|
|
|
`ifdef SDR_16 // SDR SDRAM
|
`ifdef SDR_16 // SDR SDRAM
|
wb0 wb0i
|
wb0 wb0i
|
(
|
(
|
.adr(wb0_adr_i),
|
.adr(wb0_adr_i),
|
.bte(wb0_bte_i),
|
.bte(wb0_bte_i),
|
| Line 142... |
Line 164... |
.dat_i(wb4_dat_o),
|
.dat_i(wb4_dat_o),
|
.reset(wb_rst)
|
.reset(wb_rst)
|
);
|
);
|
`endif
|
`endif
|
|
|
versatile_mem_ctrl_top dut
|
versatile_mem_ctrl_top dut (
|
(
|
// wb clk0
|
.wbs0_dat_i(wb0_dat_i),
|
.wb_dat_i_0(wb_dat_i_v),
|
.wbs0_dat_o(wb0_dat_o),
|
.wb_dat_o_0(wb_dat_o_v),
|
.wbs0_adr_i(wb0_adr_i[31:2]),
|
.wb_adr_i_0(wb_adr_i_v),
|
.wbs0_sel_i(wb0_sel_i),
|
//.wb_sel_i_0(),
|
.wbs0_cti_i(wb0_cti_i),
|
//.wb_cti_i_0(),
|
.wbs0_bte_i(wb0_bte_i),
|
//.wb_bte_i_0(),
|
.wbs0_we_i (wb0_we_i),
|
//.wb_we_i_0(),
|
.wbs0_cyc_i(wb0_cyc_i),
|
.wb_cyc_i_0(wb_cyc_i_v),
|
.wbs0_stb_i(wb0_stb_i),
|
.wb_stb_i_0(wb_stb_i_v),
|
.wbs0_ack_o(wb0_ack_o),
|
.wb_ack_o_0(wb_ack_o_v),
|
.wbs1_dat_i(wb1_dat_i),
|
// wb clk1
|
.wbs1_dat_o(wb1_dat_o),
|
/* .wb_dat_i_1(),
|
.wbs1_adr_i(wb1_adr_i[31:2]),
|
.wb_dat_o_1(),
|
.wbs1_sel_i(wb1_sel_i),
|
.wb_adr_i_1(),
|
.wbs1_cti_i(wb1_cti_i),
|
.wb_sel_i_1(),
|
.wbs1_bte_i(wb1_bte_i),
|
.wb_cti_i_1(),
|
.wbs1_we_i (wb1_we_i),
|
.wb_bte_i_1(),
|
.wbs1_cyc_i(wb1_cyc_i),
|
.wb_we_i_1(),
|
.wbs1_stb_i(wb1_stb_i),
|
.wb_cyc_i_1(),
|
.wbs1_ack_o(wb1_ack_o),
|
.wb_stb_i_1(),
|
.wbs4_dat_i(wb4_dat_i),
|
.wb_ack_o_1(), */
|
.wbs4_dat_o(wb4_dat_o),
|
// wb clk2
|
.wbs4_adr_i(wb4_adr_i[31:2]),
|
/* .wb_dat_i_2(),
|
.wbs4_sel_i(wb4_sel_i),
|
.wb_dat_o_2(),
|
.wbs4_cti_i(wb4_cti_i),
|
.wb_adr_i_2(),
|
.wbs4_bte_i(wb4_bte_i),
|
.wb_sel_i_2(),
|
.wbs4_we_i (wb4_we_i),
|
.wb_cti_i_2(),
|
.wbs4_cyc_i(wb4_cyc_i),
|
.wb_bte_i_2(),
|
.wbs4_stb_i(wb4_stb_i),
|
.wb_we_i_2(),
|
.wbs4_ack_o(wb4_ack_o),
|
.wb_cyc_i_2(),
|
|
.wb_stb_i_2(),
|
|
.wb_ack_o_2(), */
|
|
// wb clk3
|
|
/* .wb_dat_i_3(),
|
|
.wb_dat_o_3(),
|
|
.wb_adr_i_3(),
|
|
.wb_sel_i_3(),
|
|
.wb_cti_i_3(),
|
|
.wb_bte_i_3(),
|
|
.wb_we_i_3(),
|
|
.wb_cyc_i_3(),
|
|
.wb_stb_i_3(),
|
|
.wb_ack_o_3(), */
|
// SDR SDRAM 16
|
// SDR SDRAM 16
|
`ifdef SDR_16
|
`ifdef SDR_16
|
.ba_pad_o(ba),
|
.ba_pad_o(ba),
|
.a_pad_o(a),
|
.a_pad_o(a),
|
.cs_n_pad_o(cs_n),
|
.cs_n_pad_o(cs_n),
|
