| Line 3... |
Line 3... |
module versatile_mem_ctrl_tb
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module versatile_mem_ctrl_tb
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(
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(
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output OK
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output OK
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);
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);
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// number of wb clock domains
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parameter nr_of_wb_clk_domains = 1;
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// number of wb ports in each wb clock domain
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parameter nr_of_wb_ports_clk0 = 3;
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parameter nr_of_wb_ports_clk1 = 0;
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parameter nr_of_wb_ports_clk2 = 0;
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parameter nr_of_wb_ports_clk3 = 0;
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reg sdram_clk, wb_clk, wb_rst;
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reg sdram_clk, wb_clk, wb_rst;
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wire [31:0] wb0_dat_i;
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wire [31:0] wb0_dat_i;
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wire [3:0] wb0_sel_i;
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wire [3:0] wb0_sel_i;
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wire [31:0] wb0_adr_i;
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wire [31:0] wb0_adr_i;
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| Line 54... |
Line 46... |
wire [1:0] dqm, dqmd, dm_rdqs;
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wire [1:0] dqm, dqmd, dm_rdqs;
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wire dq_oe, dqs_oe;
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wire dq_oe, dqs_oe;
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wire cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;
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wire cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;
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wire ck_fb_i, ck_fb_o;
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wire ck_fb_i, ck_fb_o;
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//
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wire [36*nr_of_wb_ports_clk0-1:0] wb_dat_i_v;
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wire [36*nr_of_wb_ports_clk0-1:0] wb_adr_i_v;
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wire [31:0] wb_dat_o_v;
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wire [0:nr_of_wb_ports_clk0-1] wb_cyc_i_v;
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wire [0:nr_of_wb_ports_clk0-1] wb_stb_i_v;
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wire [0:nr_of_wb_ports_clk0-1] wb_ack_o_v;
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//
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assign wb_dat_i_v = {4'h0,wb4_dat_i,4'h0,wb1_dat_i,3'h0,wb0_dat_i};
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assign wb_adr_i_v = {4'h0,wb4_adr_i,4'h0,wb1_adr_i,3'h0,wb0_adr_i};
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assign wb_cyc_i_v = {wb4_cyc_i,wb1_cyc_i,wb0_cyc_i};
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assign wb_stb_i_v = {wb4_stb_i,wb1_stb_i,wb0_stb_i};
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assign wb_ack_o_v = {};
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`ifdef SDR_16 // SDR SDRAM
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`ifdef SDR_16 // SDR SDRAM
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wb0 wb0i
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wb0 wb0i
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(
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(
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.adr(wb0_adr_i),
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.adr(wb0_adr_i),
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.bte(wb0_bte_i),
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.bte(wb0_bte_i),
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| Line 164... |
Line 142... |
.dat_i(wb4_dat_o),
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.dat_i(wb4_dat_o),
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.reset(wb_rst)
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.reset(wb_rst)
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);
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);
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`endif
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`endif
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versatile_mem_ctrl_top dut (
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versatile_mem_ctrl_top # (
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// wb clk0
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.nr_of_wb_clk_domains(2),
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.wb_dat_i_0(wb_dat_i_v),
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.nr_of_wb_ports_clk0(2),
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.wb_dat_o_0(wb_dat_o_v),
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.nr_of_wb_ports_clk1(1),
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.wb_adr_i_0(wb_adr_i_v),
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.nr_of_wb_ports_clk2(0),
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//.wb_sel_i_0(),
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.nr_of_wb_ports_clk3(0))
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//.wb_cti_i_0(),
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dut (
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//.wb_bte_i_0(),
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.wb_adr_i_0({{wb0_adr_i[31:2],wb0_we_i,wb0_bte_i,wb0_cti_i},{wb1_adr_i[31:2],wb1_we_i,wb1_bte_i,wb1_cti_i}}),
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//.wb_we_i_0(),
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.wb_dat_i_0({{wb0_dat_i,wb0_sel_i},{wb1_dat_i,wb1_sel_i}}),
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.wb_cyc_i_0(wb_cyc_i_v),
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.wb_dat_o_0({wb0_dat_o,wb1_dat_o}),
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.wb_stb_i_0(wb_stb_i_v),
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.wb_stb_i_0({wb0_stb_i,wb1_stb_i}),
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.wb_ack_o_0(wb_ack_o_v),
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.wb_cyc_i_0({wb0_cyc_i,wb1_cyc_i}),
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// wb clk1
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.wb_ack_o_0({wb0_ack_o,wb1_ack_o}),
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.wb_dat_i_1(),
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.wb_dat_o_1(),
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.wb_adr_i_1({wb4_adr_i[31:2],wb4_we_i,wb4_bte_i,wb4_cti_i}),
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.wb_adr_i_1(),
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.wb_dat_i_1({wb4_dat_i,wb4_sel_i}),
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//.wb_sel_i_1(),
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.wb_dat_o_1(wb4_dat_o),
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//.wb_cti_i_1(),
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.wb_stb_i_1(wb4_stb_i),
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//.wb_bte_i_1(),
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.wb_cyc_i_1(wb4_cyc_i),
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//.wb_we_i_1(),
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.wb_ack_o_1(wb4_ack_o),
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.wb_cyc_i_1(),
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.wb_stb_i_1(),
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.wb_adr_i_2(2'b0),
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.wb_ack_o_1(),
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.wb_dat_i_2(2'b0),
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// wb clk2
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.wb_dat_i_2(),
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.wb_dat_o_2(),
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.wb_dat_o_2(),
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.wb_adr_i_2(),
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.wb_stb_i_2(2'b0),
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//.wb_sel_i_2(),
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.wb_cyc_i_2(2'b0),
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//.wb_cti_i_2(),
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//.wb_bte_i_2(),
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//.wb_we_i_2(),
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.wb_cyc_i_2(),
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.wb_stb_i_2(),
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.wb_ack_o_2(),
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.wb_ack_o_2(),
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// wb clk3
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.wb_dat_i_3(),
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.wb_adr_i_3(2'b0),
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.wb_dat_i_3(2'b0),
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.wb_dat_o_3(),
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.wb_dat_o_3(),
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.wb_adr_i_3(),
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.wb_stb_i_3(2'b0),
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//.wb_sel_i_3(),
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.wb_cyc_i_3(2'b0),
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//.wb_cti_i_3(),
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//.wb_bte_i_3(),
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//.wb_we_i_3(),
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.wb_cyc_i_3(),
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.wb_stb_i_3(),
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.wb_ack_o_3(),
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.wb_ack_o_3(),
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// SDR SDRAM 16
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// SDR SDRAM 16
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`ifdef SDR_16
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`ifdef SDR_16
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.ba_pad_o(ba),
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.ba_pad_o(ba),
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.a_pad_o(a),
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.a_pad_o(a),
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.cs_n_pad_o(cs_n),
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.cs_n_pad_o(cs_n),
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| Line 245... |
Line 213... |
.dqs_n_pad_io(dqs_n_io),
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.dqs_n_pad_io(dqs_n_io),
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.rdqs_n_pad_i(),
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.rdqs_n_pad_i(),
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.odt_pad_o(),
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.odt_pad_o(),
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`endif
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`endif
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// misc
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// misc
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.wb_clk(wb_clk),
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.wb_clk({wb_clk,wb_clk}),
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.wb_rst(wb_rst),
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.wb_rst({wb_rst,wb_rst}),
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.sdram_clk(sdram_clk)
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.sdram_clk(sdram_clk),
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.sdram_rst(wb_rst)
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);
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);
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`ifdef SDR_16
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`ifdef SDR_16
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assign #1 dq_io = dq_oe ? dq_o : {16{1'bz}};
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assign #1 dq_io = dq_oe ? dq_o : {16{1'bz}};
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assign #1 dq_i = dq_io;
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assign #1 dq_i = dq_io;
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